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Delayed line bus scheme: a low-power bus scheme for coupled on-chip buses

Published: 09 August 2004 Publication History

Abstract

This paper presents a comprehensive qualitative and analytical analysis of the effect of relative delay on the dissipated energy of coupled lines. Closed form expressions modeling the effect of relative delay on the dissipated energy, and the Miller coupling factor, MCF, are also presented. Skewing the worst switching case is shown to provide up to 50% reduction in energy dissipation. This observation was implemented in a low-power bus scheme, DLBS, which leads to a power reduction of up to 25%.

References

[1]
P. Sotiriadis et al., "A bus energy model for deep submicron technology," T-VLSI, vol.10-3, pp. 341--350, June 2002.
[2]
R. Kumar, "Interconnect and Noise Immunity Design for the Pentium® 4 Processor," Intel Tech. Journal, Q1, 2001.
[3]
Y. Shin et al., "Coupling-Driven Bus Design for Low-Power Application-Specific Systems," DAC'01, pp. 750--753.
[4]
Mircea R. Stan and Wayne P. Burleson, "Bus-Invert Coding for Low-Power I/O," T-VLSI, vol. 3, pp. 49--58, March 1995.
[5]
K. Hirose and H. Yassura, "A bus delay reduction technique considering crosstalk," In DATE 2000, pp.441--445.

Cited By

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  • (2022)Optical Interconnects Finally Seeing the Light in Silicon Photonics: Past the HypeNanomaterials10.3390/nano1203048512:3(485)Online publication date: 29-Jan-2022
  • (2014)On-Chip Codeword Generation to Cope With CrosstalkIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2013.228401733:2(237-250)Online publication date: 1-Feb-2014
  • (2008)Timing-aware power-optimal ordering of signalsACM Transactions on Design Automation of Electronic Systems10.1145/1391962.139197313:4(1-17)Online publication date: 3-Oct-2008
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      cover image ACM Conferences
      ISLPED '04: Proceedings of the 2004 international symposium on Low power electronics and design
      August 2004
      414 pages
      ISBN:1581139292
      DOI:10.1145/1013235
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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      Association for Computing Machinery

      New York, NY, United States

      Publication History

      Published: 09 August 2004

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      Author Tags

      1. buses
      2. coupling capacitance
      3. interconnects
      4. low power

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      ISLPED04
      Sponsor:
      ISLPED04: International Symposium on Low Power Electronics and Design
      August 9 - 11, 2004
      California, Newport Beach, USA

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      Overall Acceptance Rate 398 of 1,159 submissions, 34%

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      Cited By

      View all
      • (2022)Optical Interconnects Finally Seeing the Light in Silicon Photonics: Past the HypeNanomaterials10.3390/nano1203048512:3(485)Online publication date: 29-Jan-2022
      • (2014)On-Chip Codeword Generation to Cope With CrosstalkIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2013.228401733:2(237-250)Online publication date: 1-Feb-2014
      • (2008)Timing-aware power-optimal ordering of signalsACM Transactions on Design Automation of Electronic Systems10.1145/1391962.139197313:4(1-17)Online publication date: 3-Oct-2008
      • (2008)Encoding Techniques for On-Chip Communication ArchitecturesOn-Chip Communication Architectures10.1016/B978-0-12-373892-9.00007-4(253-300)Online publication date: 2008
      • (2006)Low-power bus encoding using an adaptive hybrid algorithmProceedings of the 43rd annual Design Automation Conference10.1145/1146909.1147158(987-990)Online publication date: 24-Jul-2006

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