Article

Probabilistic dual-Vth leakage optimization under variability

Authors:

Azadeh Davoodi,

Ankur SrivastavaAuthors Info & Claims

ISLPED '05: Proceedings of the 2005 international symposium on Low power electronics and design

Pages 143 - 148

https://doi.org/10.1145/1077603.1077641

Published: 08 August 2005 Publication History

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Abstract

In this paper we address the problem of growing leakage variability through effective dual-threshold voltage assignment. We propose a probabilistic dynamic programming-based method to assign dual-threshold voltages such that the overall expected leakage is minimized under a given probability of violating the timing constraint (timing yield). The key characteristics of our strategy are two pruning criteria that stochastically identify pareto-optimal solutions and prune the sub-optimal ones. Compared to other variability-driven dual-threshold voltage assignment schemes, the main advantages of our approach are 1) considering correlations due to common sources of variation, 2) providing controllable runtime, which in one of the proposed strategies is comparable to the deterministic algorithm, and 3) performing optimization based on all the signal paths simultaneously, as opposed to one path at a time. Experimental results indicate that the proposed probabilistic scheme is significantly better than a comparable deterministic dual-threshold voltage assignment, both in terms of expected leakage and the probability of violating the timing constraint

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Cited By

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Sauer MCzutro APolian IBecker B(2011)Estimation of component criticality in early design stepsProceedings of the 2011 IEEE 17th International On-Line Testing Symposium10.1109/IOLTS.2011.5993819(104-110)Online publication date: 13-Jul-2011
https://dl.acm.org/doi/10.1109/IOLTS.2011.5993819
Tie MDong HWang TCheng XDe Micheli GAl-Hashimi BMueller WMacii E(2010)Dual-Vth leakage reduction with fast clock skew scheduling enhancementProceedings of the Conference on Design, Automation and Test in Europe10.5555/1870926.1871049(520-525)Online publication date: 8-Mar-2010
https://dl.acm.org/doi/10.5555/1870926.1871049
Chandra SLahiri KRaghunathan ADey SLevitan S(2007)System-on-chip power management considering leakage power variationsProceedings of the 44th annual Design Automation Conference10.1145/1278480.1278696(877-882)Online publication date: 4-Jun-2007
https://dl.acm.org/doi/10.1145/1278480.1278696
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Index Terms

Probabilistic dual-Vth leakage optimization under variability
1. Hardware
  1. Hardware test
  2. Robustness
    1. Hardware reliability

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Published In

ISLPED '05: Proceedings of the 2005 international symposium on Low power electronics and design

August 2005

400 pages

ISBN:1595931376

DOI:10.1145/1077603

General Chairs:
Kaushik Roy
Purdue University
,
Vivek Tiwari
Intel

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 08 August 2005

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ISLPED05: International Symposium on Low Power Electronics and Design

August 8 - 10, 2005

CA, San Diego, USA

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Overall Acceptance Rate 398 of 1,159 submissions, 34%

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Cited By

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Sauer MCzutro APolian IBecker B(2011)Estimation of component criticality in early design stepsProceedings of the 2011 IEEE 17th International On-Line Testing Symposium10.1109/IOLTS.2011.5993819(104-110)Online publication date: 13-Jul-2011
https://dl.acm.org/doi/10.1109/IOLTS.2011.5993819
Tie MDong HWang TCheng XDe Micheli GAl-Hashimi BMueller WMacii E(2010)Dual-Vth leakage reduction with fast clock skew scheduling enhancementProceedings of the Conference on Design, Automation and Test in Europe10.5555/1870926.1871049(520-525)Online publication date: 8-Mar-2010
https://dl.acm.org/doi/10.5555/1870926.1871049
Chandra SLahiri KRaghunathan ADey SLevitan S(2007)System-on-chip power management considering leakage power variationsProceedings of the 44th annual Design Automation Conference10.1145/1278480.1278696(877-882)Online publication date: 4-Jun-2007
https://dl.acm.org/doi/10.1145/1278480.1278696
Davoodi ASrivastava AScheffer L(2006)Probabilistic evaluation of solutions in variability-driven optimizationProceedings of the 2006 international symposium on Physical design10.1145/1123008.1123013(17-24)Online publication date: 9-Apr-2006
https://dl.acm.org/doi/10.1145/1123008.1123013

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