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Article

Deterministic approaches to analog performance space exploration (PSE)

Authors:

Daniel Mueller,

Ulf SchlichtmannAuthors Info & Claims

DAC '05: Proceedings of the 42nd annual Design Automation Conference

Pages 869 - 874

https://doi.org/10.1145/1065579.1065807

Published: 13 June 2005 Publication History

Abstract

Performance space exploration (PSE) determines the range of feasible performance values of a circuit block for a given topology and technology. In this paper, we present two deterministic approaches for PSE. One approximates the feasible performance space based on linearized circuit models and is suitable for investigating a large number of performances. The other one computes discretizations of the Pareto front of competing performances. In addition, a motivation and application of PSE using a hierarchical design example is presented.

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www.muneda.com

Cited By

Kundu SMandal P(2018)An efficient method of Pareto-optimal front generation for analog circuitsAnalog Integrated Circuits and Signal Processing10.1007/s10470-017-1073-594:2(289-316)Online publication date: 1-Feb-2018
https://dl.acm.org/doi/10.1007/s10470-017-1073-5
Liu YYoshioka MHomma KShibuya TWakabayashi K(2009)Efficiently finding the 'best' solution with multi-objectives from multiple topologies in topology library of analog circuitProceedings of the 2009 Asia and South Pacific Design Automation Conference10.5555/1509633.1509752(498-503)Online publication date: 19-Jan-2009
https://dl.acm.org/doi/10.5555/1509633.1509752
Kolar JBiela JMinibock J(2009)Exploring the pareto front of multi-objective single-phase PFC rectifier design optimization - 99.2% efficiency vs. 7kW/din³ power density2009 IEEE 6th International Power Electronics and Motion Control Conference10.1109/IPEMC.2009.5289336(1-21)Online publication date: May-2009
https://doi.org/10.1109/IPEMC.2009.5289336
Show More Cited By

Index Terms

Deterministic approaches to analog performance space exploration (PSE)
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)

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We present a new technique to examine the trade-off regions of a circuit where its competing performances become "simultaneously optimal", i.e. Pareto optimal. It is based on circuit simulation, sizing rules, which capture elementary topological and ...
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Information & Contributors

Information

Published In

cover image ACM Conferences

DAC '05: Proceedings of the 42nd annual Design Automation Conference

June 2005

984 pages

ISBN:1595930582

DOI:10.1145/1065579

General Chair:
William H. Joyner
IBM Corp./SRC
,
Program Chairs:
Grant E. Martin
Tensilica, Inc.
,
Andrew B. Kahng
University of California at San Diego, CA

Copyright © 2005 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 13 June 2005

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DAC05: The 42nd Annual Design Automation Conference 2005

June 13 - 17, 2005

California, Anaheim, USA

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Citations

Cited By

Kundu SMandal P(2018)An efficient method of Pareto-optimal front generation for analog circuitsAnalog Integrated Circuits and Signal Processing10.1007/s10470-017-1073-594:2(289-316)Online publication date: 1-Feb-2018
https://dl.acm.org/doi/10.1007/s10470-017-1073-5
Liu YYoshioka MHomma KShibuya TWakabayashi K(2009)Efficiently finding the 'best' solution with multi-objectives from multiple topologies in topology library of analog circuitProceedings of the 2009 Asia and South Pacific Design Automation Conference10.5555/1509633.1509752(498-503)Online publication date: 19-Jan-2009
https://dl.acm.org/doi/10.5555/1509633.1509752
Kolar JBiela JMinibock J(2009)Exploring the pareto front of multi-objective single-phase PFC rectifier design optimization - 99.2% efficiency vs. 7kW/din³ power density2009 IEEE 6th International Power Electronics and Motion Control Conference10.1109/IPEMC.2009.5289336(1-21)Online publication date: May-2009
https://doi.org/10.1109/IPEMC.2009.5289336
Liu YYoshioka MHomma KShibuya T(2009)Efficiently finding the ‘best’ solution with multi-objectives from multiple topologies in topology library of analog circuit2009 Asia and South Pacific Design Automation Conference10.1109/ASPDAC.2009.4796529(498-503)Online publication date: Jan-2009
https://doi.org/10.1109/ASPDAC.2009.4796529
Ali SWilcock RWilson PBrown A(2008)Yield model characterization for analog integrated circuit using Pareto-optimal surface2008 15th IEEE International Conference on Electronics, Circuits and Systems10.1109/ICECS.2008.4675065(1163-1166)Online publication date: Aug-2008
https://doi.org/10.1109/ICECS.2008.4675065
Martens EGielen G(2008)Foundations of Design Flows for Analog and Mixed-Signal SystemsHigh-Level Modeling and Synthesis of Analog Integrated Systems10.1007/978-1-4020-6802-7_2(17-36)Online publication date: 2008
https://doi.org/10.1007/978-1-4020-6802-7_2
Graeb HMueller‐Gritschneder DSchlichtmann U(2008)Pareto optimization of analog circuits considering variabilityInternational Journal of Circuit Theory and Applications10.1002/cta.54437:2(283-299)Online publication date: 21-Aug-2008
https://doi.org/10.1002/cta.544
Lataire JVandersteen GPintelon RLauwereins RMadsen J(2007)Interactive presentation: Optimizing analog filter designs for minimum nonlinear distortions using multisine excitationsProceedings of the conference on Design, automation and test in Europe10.5555/1266366.1266423(267-272)Online publication date: 16-Apr-2007
https://dl.acm.org/doi/10.5555/1266366.1266423
Zinchenko LRadecker MBisogno FLipson H(2007)Multi-objective univariate marginal distribution optimisation of mixed analogue-digital signal circuitsProceedings of the 9th annual conference on Genetic and evolutionary computation10.1145/1276958.1277385(2242-2251)Online publication date: 7-Jul-2007
https://dl.acm.org/doi/10.1145/1276958.1277385
Zou JMueller DGraeb HSchlichtmann U(2007)Pareto-Front Computation and Automatic Sizing of CPPLLsProceedings of the 8th International Symposium on Quality Electronic Design10.1109/ISQED.2007.116(481-486)Online publication date: 26-Mar-2007
https://dl.acm.org/doi/10.1109/ISQED.2007.116
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