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Article

Wave-pipelined 2-slot time division multiplexed (WP/2-TDM) routing

Authors:

Jeffrey DavisAuthors Info & Claims

GLSVLSI '05: Proceedings of the 15th ACM Great Lakes symposium on VLSI

Pages 446 - 451

https://doi.org/10.1145/1057661.1057768

Published: 17 April 2005 Publication History

Abstract

The ever-increasing number of transistors on a chip has resulted in very large scale integration (VLSI) systems whose performance and manufacturing costs are driven by on-chip wiring needs. This paper proposes a low overhead wave-pipelined two-slot time division multiplexed (WP/2-TDM) routing technique that harnesses the inherent intra-clock period wire idleness to implement wire sharing in combination with wave-pipelined circuit techniques. It is illustrated in this paper that WP/2-TDM routing can be readily incorporated into future gigascale integration (GSI) systems to reduce the number of interconnect routing channels in an attempt to contain escalating manufacturing costs. Two case studies, one at the circuit level and one at the system level, are presented to illustrate the advantages of WP/2-TDM routing. The circuit level implementation exhibits more than 40% reduction in wire area, a 30% reduction in silicon area with no increase in dynamic power and no loss of throughput performance.

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Cited By

Joshi ADavis J(2005)Gigascale ASIC/SoC design using wave-pipelined multiplexed (WPM) routing2005 Joint 30th International Conference on Infrared and Millimeter Waves and 13th International Conference on Terahertz Electronics10.1109/SOCC.2005.1554481(137-142)Online publication date: 2005
https://doi.org/10.1109/SOCC.2005.1554481

Index Terms

Wave-pipelined 2-slot time division multiplexed (WP/2-TDM) routing
1. Hardware
  1. Very large scale integration design
    1. VLSI system specification and constraints

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Information

Published In

cover image ACM Conferences

GLSVLSI '05: Proceedings of the 15th ACM Great Lakes symposium on VLSI

April 2005

518 pages

ISBN:1595930574

DOI:10.1145/1057661

General Chair:
John Lach
University of Virginia
,
Program Chairs:
Gang Qu
University of Maryland, College Park
,
Yehea Ismail
Northwestern University

Copyright © 2005 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 17 April 2005

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GLSVLSI05

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GLSVLSI05: Great Lakes Symposium on VLSI 2005

April 17 - 19, 2005

Illinois, Chicago, USA

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Overall Acceptance Rate 312 of 1,156 submissions, 27%

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Cited By

Joshi ADavis J(2005)Gigascale ASIC/SoC design using wave-pipelined multiplexed (WPM) routing2005 Joint 30th International Conference on Infrared and Millimeter Waves and 13th International Conference on Terahertz Electronics10.1109/SOCC.2005.1554481(137-142)Online publication date: 2005
https://doi.org/10.1109/SOCC.2005.1554481

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