Article

Causal probabilistic input dependency learning for switching model in VLSI circuits

Authors:

Nirmal Ramalingam,

Sanjukta BhanjaAuthors Info & Claims

GLSVLSI '05: Proceedings of the 15th ACM Great Lakes symposium on VLSI

Pages 112 - 115

https://doi.org/10.1145/1057661.1057689

Published: 17 April 2005 Publication History

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Abstract

Switching model captures the data-driven uncertainty in logic circuits in a comprehensive probabilistic framework. Switching is a critical factor that influences dynamic, active leakage power, coupling noises in CMOS implementations. In this work, we model the input-space by a causal graphical probabilistic model that encapsulates the dependencies in inputs in a compact, minimal fashion and also allows for instantiations of the vector-space that closely match the underlying dependencies, with the constraint that the reduced vector-space captures the dependencies in the larger dataset accu-rately. Results on ISCAS benchmark show that average error is limited to 1.8% while we achieve a compaction ratio of 300.

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Ayupov ABurns SPhillips JHu AGraeb H(2011)A trace compression algorithm targeting power estimation of long benchmarksProceedings of the International Conference on Computer-Aided Design10.5555/2132325.2132480(702-707)Online publication date: 7-Nov-2011
https://dl.acm.org/doi/10.5555/2132325.2132480
Ayupov ABurns S(2011)A trace compression algorithm targeting power estimation of long benchmarksProceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design10.1109/ICCAD.2011.6105406(702-707)Online publication date: 7-Nov-2011
https://dl.acm.org/doi/10.1109/ICCAD.2011.6105406
Beg AChandana Prasad P(2010)Prediction of area and length complexity measures for binary decision diagramsExpert Systems with Applications: An International Journal10.1016/j.eswa.2009.09.00337:4(2864-2873)Online publication date: 1-Apr-2010
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Index Terms

Causal probabilistic input dependency learning for switching model in VLSI circuits
1. Hardware
  1. Hardware validation

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Information

Published In

GLSVLSI '05: Proceedings of the 15th ACM Great Lakes symposium on VLSI

April 2005

518 pages

ISBN:1595930574

DOI:10.1145/1057661

General Chair:
John Lach
University of Virginia
,
Program Chairs:
Gang Qu
University of Maryland, College Park
,
Yehea Ismail
Northwestern University

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 17 April 2005

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GLSVLSI05

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GLSVLSI05: Great Lakes Symposium on VLSI 2005

April 17 - 19, 2005

Illinois, Chicago, USA

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Overall Acceptance Rate 312 of 1,156 submissions, 27%

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Cited By

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Ayupov ABurns SPhillips JHu AGraeb H(2011)A trace compression algorithm targeting power estimation of long benchmarksProceedings of the International Conference on Computer-Aided Design10.5555/2132325.2132480(702-707)Online publication date: 7-Nov-2011
https://dl.acm.org/doi/10.5555/2132325.2132480
Ayupov ABurns S(2011)A trace compression algorithm targeting power estimation of long benchmarksProceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design10.1109/ICCAD.2011.6105406(702-707)Online publication date: 7-Nov-2011
https://dl.acm.org/doi/10.1109/ICCAD.2011.6105406
Beg AChandana Prasad P(2010)Prediction of area and length complexity measures for binary decision diagramsExpert Systems with Applications: An International Journal10.1016/j.eswa.2009.09.00337:4(2864-2873)Online publication date: 1-Apr-2010
https://dl.acm.org/doi/10.1016/j.eswa.2009.09.003
Chandana Prasad PBeg A(2009)Investigating data preprocessing methods for circuit complexity modelsExpert Systems with Applications: An International Journal10.1016/j.eswa.2007.09.05236:1(519-526)Online publication date: 1-Jan-2009
https://dl.acm.org/doi/10.1016/j.eswa.2007.09.052
Beg AChandana Prasad PBeg A(2008)Applicability of feed-forward and recurrent neural networks to Boolean function complexity modelingExpert Systems with Applications: An International Journal10.1016/j.eswa.2007.04.01034:4(2436-2443)Online publication date: 1-May-2008
https://dl.acm.org/doi/10.1016/j.eswa.2007.04.010
Prasad PBeg A(2007)A methodology for evaluation time approximation2007 50th Midwest Symposium on Circuits and Systems10.1109/MWSCAS.2007.4488692(776-778)Online publication date: Aug-2007
https://doi.org/10.1109/MWSCAS.2007.4488692
Prasad PAssi ABeg A(2007)Binary Decision Diagrams and neural networksThe Journal of Supercomputing10.1007/s11227-006-0010-739:3(301-320)Online publication date: 1-Mar-2007
https://dl.acm.org/doi/10.1007/s11227-006-0010-7
Prasad PAssi AMills B(2006)Binary decision diagramsProceedings of the 6th WSEAS International Conference on Simulation, Modelling and Optimization10.5555/1369472.1369504(179-185)Online publication date: 22-Sep-2006
https://dl.acm.org/doi/10.5555/1369472.1369504
Mohammad MTerkawi LAlbasman M(2006)A Stimulus-Free Probabilistic Model for Single-Event-Upset SensitivityProceedings of the 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design10.1109/VLSID.2006.26(100-107)Online publication date: 3-Jan-2006
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Rejimon TBhanja S(2006)A timing-aware probabilistic model for single-event-upset analysisIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2006.88416514:10(1130-1139)Online publication date: 1-Oct-2006
https://dl.acm.org/doi/10.1109/TVLSI.2006.884165
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