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Article

Interconnect delay minimization through interlayer via placement in 3-D ICs

Authors:

Vasilis F. Pavlidis,

Eby G. FriedmanAuthors Info & Claims

GLSVLSI '05: Proceedings of the 15th ACM Great Lakes symposium on VLSI

Pages 20 - 25

https://doi.org/10.1145/1057661.1057669

Published: 17 April 2005 Publication History

Abstract

The dependence of the propagation delay of the interlayer 3-D interconnects on the vertical through via location and length is investigated. For a variable vertical through via location, with fixed vertical length, the optimum vertical through via location that minimizes the propagation delay of an interconnect line connecting two circuits on different planes is determined. The optimum vertical through via location and length or, equivalently, the number of physical planes traversed by the vertical through via, are determined for varying the placement of the connected circuits. Design expressions for the optimal via locations and lengths have been developed to support placement and routing algorithms for 3-D ICs.

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Cited By

Panem CGad RRane UGad V(2018)Evaluation of 3D & 4D Two Layer Mesh NoC for Fault Tolerance over Combinations of Vertical Channel2018 International Conference on Current Trends towards Converging Technologies (ICCTCT)10.1109/ICCTCT.2018.8551081(1-7)Online publication date: Mar-2018
https://doi.org/10.1109/ICCTCT.2018.8551081
Pandiaraj KSivakumar PGeetharamani N(2017)Reduction of temperature rise in 3D IC routing2017 IEEE International Conference on Electrical, Instrumentation and Communication Engineering (ICEICE)10.1109/ICEICE.2017.8191907(1-5)Online publication date: Apr-2017
https://doi.org/10.1109/ICEICE.2017.8191907
Pangracious VMarrakchi ZMehrez HPangracious VMarrakchi ZMehrez H(2015)Three-Dimensional Integration: A More Than Moore TechnologyThree-Dimensional Design Methodologies for Tree-based FPGA Architecture10.1007/978-3-319-19174-4_2(13-41)Online publication date: 26-Jun-2015
https://doi.org/10.1007/978-3-319-19174-4_2
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Index Terms

Interconnect delay minimization through interlayer via placement in 3-D ICs
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)

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Information

Published In

cover image ACM Conferences

GLSVLSI '05: Proceedings of the 15th ACM Great Lakes symposium on VLSI

April 2005

518 pages

ISBN:1595930574

DOI:10.1145/1057661

General Chair:
John Lach
University of Virginia
,
Program Chairs:
Gang Qu
University of Maryland, College Park
,
Yehea Ismail
Northwestern University

Copyright © 2005 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 17 April 2005

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GLSVLSI05

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GLSVLSI05: Great Lakes Symposium on VLSI 2005

April 17 - 19, 2005

Illinois, Chicago, USA

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Overall Acceptance Rate 312 of 1,156 submissions, 27%

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Cited By

Panem CGad RRane UGad V(2018)Evaluation of 3D & 4D Two Layer Mesh NoC for Fault Tolerance over Combinations of Vertical Channel2018 International Conference on Current Trends towards Converging Technologies (ICCTCT)10.1109/ICCTCT.2018.8551081(1-7)Online publication date: Mar-2018
https://doi.org/10.1109/ICCTCT.2018.8551081
Pandiaraj KSivakumar PGeetharamani N(2017)Reduction of temperature rise in 3D IC routing2017 IEEE International Conference on Electrical, Instrumentation and Communication Engineering (ICEICE)10.1109/ICEICE.2017.8191907(1-5)Online publication date: Apr-2017
https://doi.org/10.1109/ICEICE.2017.8191907
Pangracious VMarrakchi ZMehrez HPangracious VMarrakchi ZMehrez H(2015)Three-Dimensional Integration: A More Than Moore TechnologyThree-Dimensional Design Methodologies for Tree-based FPGA Architecture10.1007/978-3-319-19174-4_2(13-41)Online publication date: 26-Jun-2015
https://doi.org/10.1007/978-3-319-19174-4_2
Ghidini YWebbed TMoreno EQuadros IFagundes RMarcon C(2012)Topological impact on latency and throughput: 2D versus 3D NoC comparison2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI)10.1109/SBCCI.2012.6344439(1-6)Online publication date: Aug-2012
https://doi.org/10.1109/SBCCI.2012.6344439
Qian LZhu ZYang Y(2012)Through-silicon-via insertion for performance optimization in three-dimensional integrated circuitsMicroelectronics Journal10.1016/j.mejo.2011.11.00443:2(128-133)Online publication date: Feb-2012
https://doi.org/10.1016/j.mejo.2011.11.004
Lim SLim S(2012)Steiner Routing for 3D ICDesign for High Performance, Low Power, and Reliable 3D Integrated Circuits10.1007/978-1-4419-9542-1_2(41-73)Online publication date: 24-Sep-2012
https://doi.org/10.1007/978-1-4419-9542-1_2
Lim SLim S(2012)Multi-objective Architectural Floorplanning for 3D ICDesign for High Performance, Low Power, and Reliable 3D Integrated Circuits10.1007/978-1-4419-9542-1_10(253-283)Online publication date: 24-Sep-2012
https://doi.org/10.1007/978-1-4419-9542-1_10
Hsieh KCheng BGu RLi K(2011)Fault-tolerant mesh for 3D network on chip2011 6th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)10.1109/IMPACT.2011.6117292(202-205)Online publication date: Oct-2011
https://doi.org/10.1109/IMPACT.2011.6117292
Pavlidis VFriedman E(2010)Physical Design Issues in 3-D Integrated TechnologiesVLSI-SoC: Design Methodologies for SoC and SiP10.1007/978-3-642-12267-5_1(1-21)Online publication date: 2010
https://doi.org/10.1007/978-3-642-12267-5_1
Pathak MLim S(2009)Performance and thermal-aware Steiner routing for 3-D stacked ICsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2009.202470728:9(1373-1386)Online publication date: 1-Sep-2009
https://dl.acm.org/doi/10.1109/TCAD.2009.2024707
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