Article

Understanding the effects of wrong-path memory references on processor performance

Authors:

Onur Mutlu,

Hyesoon Kim,

David N. Armstrong,

Yale N. PattAuthors Info & Claims

WMPI '04: Proceedings of the 3rd workshop on Memory performance issues: in conjunction with the 31st international symposium on computer architecture

Pages 56 - 64

https://doi.org/10.1145/1054943.1054951

Published: 20 June 2004 Publication History

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Abstract

High-performance out-of-order processors spend a significant portion of their execution time on the incorrect program path even though they employ aggressive branch prediction algorithms. Although memory references generated on the wrong path do not change the architectural state of the processor, they can affect the arrangement of data in the memory hierarchy. This paper examines the effects of wrong-path memory references on processor performance. It is shown that these references significantly affect the IPC (Instructions Per Cycle) performance of a processor. Not modeling them can lead to errors of up to 10% in IPC estimates for the SPEC2000 integer benchmarks; 7 out of 12 benchmarks experience an error of greater than 2% in IPC estimates. In general, the error in the IPC increases with increasing memory latency and instruction window size.We find that wrong-path references are usually beneficial for performance, because they prefetch data that will be used by later correct-path references. L2 cache pollution is found to be the most significant negative effect of wrong-path references. Code examples are shown to provide insights into how wrong-path references affect performance.

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Ros AJimborean A(2024)Wrong-Path-Aware Entangling Instruction PrefetcherIEEE Transactions on Computers10.1109/TC.2023.333730873:2(548-559)Online publication date: Feb-2024
https://doi.org/10.1109/TC.2023.3337308
Tang BWu CWang ZJia LYew PCheng YZhang YWang CXu G(2023)SpecBox: A Label-Based Transparent Speculation Scheme Against Transient Execution AttacksIEEE Transactions on Dependable and Secure Computing10.1109/TDSC.2022.314428720:1(827-840)Online publication date: 1-Jan-2023
https://doi.org/10.1109/TDSC.2022.3144287
Hashemi MPatt YPrvulovic M(2015)Filtered runahead execution with a runahead bufferProceedings of the 48th International Symposium on Microarchitecture10.1145/2830772.2830812(358-369)Online publication date: 5-Dec-2015
https://dl.acm.org/doi/10.1145/2830772.2830812
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Understanding the effects of wrong-path memory references on processor performance

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Published In

WMPI '04: Proceedings of the 3rd workshop on Memory performance issues: in conjunction with the 31st international symposium on computer architecture

June 2004

146 pages

ISBN:159593040X

DOI:10.1145/1054943

Conference Chairs:
John Carter
University of Utah
,
Lixin Zhang
IBM Austin Research Lab

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Association for Computing Machinery

New York, NY, United States

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Published: 20 June 2004

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Ros AJimborean A(2024)Wrong-Path-Aware Entangling Instruction PrefetcherIEEE Transactions on Computers10.1109/TC.2023.333730873:2(548-559)Online publication date: Feb-2024
https://doi.org/10.1109/TC.2023.3337308
Tang BWu CWang ZJia LYew PCheng YZhang YWang CXu G(2023)SpecBox: A Label-Based Transparent Speculation Scheme Against Transient Execution AttacksIEEE Transactions on Dependable and Secure Computing10.1109/TDSC.2022.314428720:1(827-840)Online publication date: 1-Jan-2023
https://doi.org/10.1109/TDSC.2022.3144287
Hashemi MPatt YPrvulovic M(2015)Filtered runahead execution with a runahead bufferProceedings of the 48th International Symposium on Microarchitecture10.1145/2830772.2830812(358-369)Online publication date: 5-Dec-2015
https://dl.acm.org/doi/10.1145/2830772.2830812
Velásquez RMichaud PSeznec A(2015)BADCOInternational Journal of Parallel Programming10.1007/s10766-013-0278-143:1(130-157)Online publication date: 1-Feb-2015
https://dl.acm.org/doi/10.1007/s10766-013-0278-1
Eeckhout L(2010)Computer Architecture Performance Evaluation MethodsSynthesis Lectures on Computer Architecture10.2200/S00273ED1V01Y201006CAC0105:1(1-145)Online publication date: 22-Dec-2010
https://doi.org/10.2200/S00273ED1V01Y201006CAC010
La Fratta PKogge PAmato NFranke HKelly P(2010)Models for generating locality-tuned traveling threads for a hierarchical multi-level heterogeneous multicoreProceedings of the 7th ACM international conference on Computing frontiers10.1145/1787275.1787329(227-236)Online publication date: 17-May-2010
https://dl.acm.org/doi/10.1145/1787275.1787329
Eeckhout L(2008)Sampled Processor Simulation: A SurveyAdvances in COMPUTERS - High Performance Computing10.1016/S0065-2458(08)00004-1(173-224)Online publication date: 2008
https://doi.org/10.1016/S0065-2458(08)00004-1
Sendag RYilmazer AYi JUht A(2007)The impact of wrong-path memory references in cache-coherent multiprocessor systemsJournal of Parallel and Distributed Computing10.1016/j.jpdc.2007.03.00567:12(1256-1269)Online publication date: 1-Dec-2007
https://dl.acm.org/doi/10.1016/j.jpdc.2007.03.005
Sendag RYilmazer AYi JUht A(2006)Quantifying and reducing the effects of wrong-path memory references in cache-coherent multiprocessor systemsProceedings of the 20th international conference on Parallel and distributed processing10.5555/1898953.1898957(21-21)Online publication date: 25-Apr-2006
https://dl.acm.org/doi/10.5555/1898953.1898957
Enright Jerger NHill ELipasti M(2006)Friendly fire: understanding the effects of multiprocessor prefetches2006 IEEE International Symposium on Performance Analysis of Systems and Software10.1109/ISPASS.2006.1620802(177-188)Online publication date: 2006
https://doi.org/10.1109/ISPASS.2006.1620802
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