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Intel® atom™ processor core made FPGA-synthesizable

Authors:

Jamison D. Collins,

Christopher T. Weaver,

Blliappa Kuttanna,

Shahram Salamian,

Gautham N. Chinya,

Ethan Schuchman,

Oliver Schilling,

Sebastian Steibl,

Hong WangAuthors Info & Claims

FPGA '09: Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays

Pages 209 - 218

https://doi.org/10.1145/1508128.1508160

Published: 22 February 2009 Publication History

Abstract

We present an FPGA-synthesizable version of the Intel Atom processor core, synthesized to a Virtex-5 based FPGA emulation system. To make the production Atom design in SystemVerilog synthesizable through industry standard EDA tool flow, we transformed and mapped latches in the design, converted clock gating, and replaced nonsynthesizable constructs with FPGA-synthesizable counterparts. Additionally, as the target FPGA emulator is hosted on a PC platform with the Pentium-based CPU socket that supports a significantly different front side bus (FSB) protocol from that of the Atom processor, we replaced the existing bus control logic in the Atom core with an alternate FSB protocol to communicate with the rest of the PC platform. With these efforts, we succeeded in synthesizing the entire Atom processor core to fit within a single Virtex-5 LX330 FPGA. The synthesizable Atom core runs at 50Mhz on the Pentium PC motherboard with fully functional I/O peripherals. It is capable of booting off-the-shelf MS-DOS, Windows XP and Linux operating systems, and executing standard x86 workloads.

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Cited By

Lan MHuang LYang LMa SYan RWang YXu W(2022)Late-Stage Optimization of Modern ILP Processor Cores via FPGA SimulationApplied Sciences10.3390/app12231222512:23(12225)Online publication date: 29-Nov-2022
https://doi.org/10.3390/app122312225
Podobas ASano KMatsuoka S(2020)A Survey on Coarse-Grained Reconfigurable Architectures From a Performance PerspectiveIEEE Access10.1109/ACCESS.2020.30120848(146719-146743)Online publication date: 2020
https://doi.org/10.1109/ACCESS.2020.3012084
Jain ALloyd SGokhale M(2018)Microscope on Memory: MPSoC-Enabled Computer Memory System Assessments2018 IEEE 26th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)10.1109/FCCM.2018.00035(173-180)Online publication date: Apr-2018
https://doi.org/10.1109/FCCM.2018.00035
Show More Cited By

Index Terms

Intel® atom™ processor core made FPGA-synthesizable
1. Computer systems organization
  1. Architectures

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Published In

cover image ACM Conferences

FPGA '09: Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays

February 2009

302 pages

ISBN:9781605584102

DOI:10.1145/1508128

General Chair:
Paul Chow
University of Toronto, Canada
,
Program Chair:
Peter Cheung
Imperial College London, UK

Copyright © 2009 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 22 February 2009

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FPGA '09

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FPGA '09: ACM/SIGDA International Symposium on Field Programmable Gate Arrays

February 22 - 24, 2009

California, Monterey, USA

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Overall Acceptance Rate 125 of 627 submissions, 20%

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Cited By

Lan MHuang LYang LMa SYan RWang YXu W(2022)Late-Stage Optimization of Modern ILP Processor Cores via FPGA SimulationApplied Sciences10.3390/app12231222512:23(12225)Online publication date: 29-Nov-2022
https://doi.org/10.3390/app122312225
Podobas ASano KMatsuoka S(2020)A Survey on Coarse-Grained Reconfigurable Architectures From a Performance PerspectiveIEEE Access10.1109/ACCESS.2020.30120848(146719-146743)Online publication date: 2020
https://doi.org/10.1109/ACCESS.2020.3012084
Jain ALloyd SGokhale M(2018)Microscope on Memory: MPSoC-Enabled Computer Memory System Assessments2018 IEEE 26th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)10.1109/FCCM.2018.00035(173-180)Online publication date: Apr-2018
https://doi.org/10.1109/FCCM.2018.00035
Bachrach JMagyar ADabbelt PLi PLin RAsanovic KParameswaran S(2017)CyclistProceedings of the 36th International Conference on Computer-Aided Design10.5555/3199700.3199840(1011-1018)Online publication date: 13-Nov-2017
https://dl.acm.org/doi/10.5555/3199700.3199840
Bachrach JMagyar ADabbelt PLi PLin RAsanovic K(2017)Cyclist: Accelerating hardware development2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)10.1109/ICCAD.2017.8203892(1011-1018)Online publication date: Nov-2017
https://doi.org/10.1109/ICCAD.2017.8203892
Wong HBetz VRose J(2016)Microarchitecture and Circuits for a 200 MHz Out-of-Order Soft Processor Memory SystemACM Transactions on Reconfigurable Technology and Systems10.1145/297402210:1(1-22)Online publication date: 9-Dec-2016
https://dl.acm.org/doi/10.1145/2974022
Matthews EShannon LFedorova A(2016)Shared Memory Multicore MicroBlaze System with SMP Linux SupportACM Transactions on Reconfigurable Technology and Systems10.1145/28706389:4(1-22)Online publication date: 9-Aug-2016
https://dl.acm.org/doi/10.1145/2870638
Gallardo RHu AIvanov AMirian MMarculescu DLiu F(2015)Reducing Post-Silicon Coverage Monitoring Overhead with Emulation and Bayesian Feature SelectionProceedings of the IEEE/ACM International Conference on Computer-Aided Design10.5555/2840819.2840933(816-823)Online publication date: 2-Nov-2015
https://dl.acm.org/doi/10.5555/2840819.2840933
Ogawa EMatsuda YMisono TKobayashi RKise K(2015)Reconfigurable IBM PC Compatible SoC for Computer Architecture Education and ResearchProceedings of the 2015 IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip10.1109/MCSoC.2015.35(65-72)Online publication date: 23-Sep-2015
https://dl.acm.org/doi/10.1109/MCSoC.2015.35
Gallardo RHuy AIvanov AMirian M(2015)Reducing post-silicon coverage monitoring overhead with emulation and Bayesian feature selection2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)10.1109/ICCAD.2015.7372655(816-823)Online publication date: Nov-2015
https://doi.org/10.1109/ICCAD.2015.7372655
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