[go: up one dir, main page]
More Web Proxy on the site http://driver.im/ Skip to main content
Springer Nature Link
Log in

Development of DSL Compilers for Specialized Processors

  • Published:
Programming and Computer Software Aims and scope Submit manuscript

Abstract

Modern computer systems often include specialized processors that are programmed in domain-specific languages. The compiler-in-the-loop technology, which assumes the joint development of the dedicated processor and compiler, gains in popularity. In this case, the conventional tools (such as GCC and LLVM) are insufficient for the rapid development of optimizing compilers that generate the target code for irregular architectures and static parallelism of operations. In this paper, it is proposed to use methods for solving NP-complete problems for the implementation of machine-dependent compilation phases. These phases are based on the reduction to the SMT problem, which makes it possible to get rid of heuristic and approximate approaches that require complicated software implementation. In particular, it is proposed to implement the synthesis of machine-dependent optimization rules, instruction selection, instruction scheduling, and register allocation using an SMT solver. Practical applications of the developed methods and algorithms are illustrated by the example of a compiler for a specialized processor with an instruction set that accelerates the implementation of lightweight cryptography algorithms on the Internet of Things. The results of compilation and simulation of eight cryptographic primitives for three variants of the specialized processor (CISC-like, VLIW-like and a variant with delayed load instruction) show the practical usefulness of the proposed approach.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Subscribe and save

Springer+ Basic
£29.99 /Month
  • Get 10 units per month
  • Download Article/Chapter or eBook
  • 1 Unit = 1 Article or 1 Chapter
  • Cancel anytime
Subscribe now

Buy Now

Price includes VAT (United Kingdom)

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1.
Fig. 2.
Fig. 3.
Fig 4.
Fig. 5.
Fig. 6.
Fig. 7.
Fig. 8.

Similar content being viewed by others

Explore related subjects

Discover the latest articles, news and stories from top researchers in related subjects.

REFERENCES

  1. Hennessy, J.L. and Patterson, D.A., “A new golden age for computer architecture, Commun. ACM, 2019, vol. 62, no. 2, pp. 48–60.

    Article  Google Scholar 

  2. Sampson, A., Bornholt, J., and Ceze, L., Hardware-software co-design: not just a cliche, Leibniz Int. Proc. Inform, 2015, vol. 32, pp. 262–273.

    MathSciNet  Google Scholar 

  3. Roselli, S.F., Bengtsson, K., and Akesson, K., SMT solvers for job-shop scheduling problems: Models comparison and performance evaluation, Proc. of the IEEE 14th Int. Conf. on Automation Science and Engineering (CASE), 2018, pp. 547–552.

  4. Braun, M., Buchwald, S., Hack, S., Leißa, R., Mallon, C., and Zwinkau, A., Simple and efficient construction of static single assignment form, Lect. Notes Comput, Sci., 2018, vol. 7791, pp. 102–122.

    Article  Google Scholar 

  5. Gulwani, S., Jha, S., Tiwari, A., and Venkatesan, R., Synthesis of loop-free programs, ACM SIGPLAN Notices, 2011, vol. 46, no. 6, pp. 62–73.

    Article  Google Scholar 

  6. Bjorner, N., Phan, A.D., and Fleckenstein, L., vZ—an optimizing SMT solver. Lect. Notes Comput. Sci., 2015, vol. 9035, pp.194–199.

    Article  Google Scholar 

  7. Sebastiani, R. and Tomasi, S., Optimization in SMT with LA(Q) Cost Functions, Lect. Notes Comput. Sci., 2012, vol. 7364, pp. 484–498.

    MATH  Google Scholar 

  8. Almeida, J.B. Barbosa, M., et al., Jasmin: High-assurance and high-speed cryptography, Proc. of the ACM SIGSAC Conf. on Computer and Communications Security, 2017, pp.1807–1823.

  9. Elizarov, S.G., Markov, D.S., and Sovetov, P.N., RF Patent No. 2681702, 2019.

  10. Biryukov, A. and Perrin, L.P., State of the art in lightweight symmetric cryptography, Cryptology ePrint Archive: Report, 2017/511, 2017.

  11. Massalin, H., Superoptimizer: A look at the smallest program, ACM SIGARCH Comput. Architecture News, 1987, vol. 15, no. 5, pp. 122–126.

    Article  Google Scholar 

  12. Phothilimthana, P.M., Jelvis, T., Shah, R., Totla, N., Chasins, S., and Bodik, R., Chlorophyll: Synthesis-aided compiler for low-power spatial architectures. ACM SIGPLAN Notices, 2014, vol. 49, no. 6.

  13. Buchwald, S., Optgen: A generator for local optimizations, Lect. Notes Comput. Sci., 2015, vol. 9031, pp.171–189.

    Article  Google Scholar 

  14. Sasnauskas R., Chen Y. et al., Souper: A synthesizing superoptimizer, arXiv preprint arXiv:1711.04422, 2017.

  15. Kjellin, M., Adapting a constraint-based compiler tool to a new VLIW architecture, Master’s thesis, Uppsala University, 2018.

  16. Koes, D.R. and Goldstein, S.C., Near-optimal instruction selection on DAGs. Proc. of the of the 6th Annual IEEE/ACM Int. Symposium on Code Generation and Optimization, 2008, pp. 45–54.

  17. Buchwald, S. and Zwinkau, A., Instruction selection by graph transformation, Proc. of the Int. Conf. on Compilers, Architectures and Synthesis for Embedded Systems, 2010, pp. 31–40.

  18. Blindell, G.H., Carlsson, M., Lozano, R.C., and Schulte, C., Complete and practical universal instruction selection, ACM Trans. Embedded Comput. Syst. (TECS), 2017, vol. 16, no. 5, pp. 1–18.

    Article  Google Scholar 

  19. Frolov, N., Själander, M., Larsson-Edefors, P., and McKee, S.A., Declarative, SAT-solver-based scheduling for an embedded architecture with a flexible datapath, Proc. of the, of the 11th Swedish System-on-Chip Conference, 2011.

  20. Wilken, K., Liu, J., and Heffernan, M., Optimal instruction scheduling using integer programming, ACM SIGPLAN Notices, 2000, vol. 35, no. 5, 121–133.

    Article  Google Scholar 

  21. Malik, A.M., McInnes, J., and Van Beek, P., Optimal basic block instruction scheduling for multiple-issue processors using constraint programming, Int. J. Artif. Intell. Tools, 2008, vol. 17, no. 01, pp.37–54.

    Article  Google Scholar 

  22. Ershov, A.P., Reduction of the problem of memory allocation in programming to the problem of coloring the vertices of graphs, Sov. Math. 1962, vol. 3, pp. 163–165.

    MATH  Google Scholar 

  23. Quintao, PereiraF.M. and Palsberg, J., Register allocation by puzzle solving, Proc. of the 29th ACM SIGPLAN Conference on Programming Language Design and Implementation, 2008, pp. 216–226.

  24. Fu, C. and Wilken, K., A faster optimal register allocator, Proc. of the 35th Annual IEEE/ACM Int. Symposium on Microarchitecture, 2002, pp. 245-256.

  25. Buchwald, S., Zwinkau, A., and Bersch, T., SSA-based register allocation with PBQP, Lect. Notes Comp. Sci., 2011, vol. 6601. pp. 42–61.

    Article  Google Scholar 

  26. Vyukova, N.I., Galatenko, V.A., and Samborskij, S.V., Code generation by exact joint solution of the instruction selection and scheduling tasks, Program. Inzh., 2014, no. 6, pp. 8–15.

  27. Chang, C.M., Chen, C.M., and King, C.T., Using integer linear programming for instruction scheduling and register allocation in multi-issue processors, Comput. Math. Appl., 1997, vol. 34, no. 9, pp. 1–14.

    Article  MathSciNet  Google Scholar 

  28. Lozano, R.C., Carlsson, M., Blindell, G.H., and Schulte, C., Combinatorial register allocation and instruction scheduling, ACM Trans. Program. Lang. Syst. (TOPLAS), 2019, vol. 41, no. 3, pp. 1–53.

    Article  Google Scholar 

  29. Eriksson, M. and Kessler, C., Integrated code generation for loops, ACM Trans. Embedded Comput. Syst. (TECS), 2012, vol. 11, no. 1, pp. 1–24.

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

  1. MIREA – Russian Technological University, 119454, Moscow, Russia

    P. N. Sovetov

Authors
  1. P. N. Sovetov
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to P. N. Sovetov.

Additional information

Translated by A. Klimontovich

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Sovetov, P.N. Development of DSL Compilers for Specialized Processors. Program Comput Soft 47, 541–554 (2021). https://doi.org/10.1134/S0361768821070082

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1134/S0361768821070082

Search

Navigation