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Investigation of RISC-V

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Abstract

An instruction set architecture (ISA) is a core around which the rest of a CPU is built. Errors or inflexible solutions once embedded in an instruction set remain with a corresponding generation of processors forever. Hence, one of the key reasons why the growth in the performance of modern CPUs slowed down is that the source code of processors “got corrupted” literally and figuratively: processors become more complex, which makes their further development more difficult. In any case, the development of modern computers (CPUs, GPUs, or specialized systems) is an extremely expensive process, which involves a large number of expensive stages. Therefore, the overall cost of CPU development is a key issue. In this paper, we investigate popular instruction set architectures, as well as make some conclusions about the prospects of RISC-V and other open-source architectures. We try to answer the following questions. Why an instruction set architecture is really important? Why RISC-V is better than the other architectures? Which opportunities does RISC-V open for developers around the world and what competitors does it have?

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Authors and Affiliations

  1. Keldysh Institute of Applied Mathematics, Russian Academy of Sciences, Miusskaya pl. 4, 125047, Moscow, Russia

    V. A. Frolov & V. A. Galaktionov

  2. Moscow State University, 119991, Moscow, Russia

    V. A. Frolov & V. V. Sanzharov

Authors
  1. V. A. Frolov
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  2. V. A. Galaktionov
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  3. V. V. Sanzharov
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Corresponding authors

Correspondence to V. A. Frolov, V. A. Galaktionov or V. V. Sanzharov.

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Translated by Yu. Kornienko

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Frolov, V.A., Galaktionov, V.A. & Sanzharov, V.V. Investigation of RISC-V. Program Comput Soft 47, 493–504 (2021). https://doi.org/10.1134/S0361768821070045

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  • DOI: https://doi.org/10.1134/S0361768821070045

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