Design and Implementation of a Non-pipelined MD5 Hardware Architecture Using a New Functional Description

Regular Section

The Institute of Electronics, Information and Communication Engineers">Ignacio ALGREDO-BADILLO, Claudia FEREGRINO-URIBE, René CUMPLIDO, The Institute of Electronics, Information and Communication Engineers">Miguel MORALES-SANDOVAL

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Keywords: MD5 algorithm, hardware design, FPGA implementation, hardware architectures

JOURNAL FREE ACCESS

2008 Volume E91.D Issue 10 Pages 2519-2523

DOI https://doi.org/10.1093/ietisy/e91-d.10.2519

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Abstract

MD5 is a cryptographic algorithm used for authentication. When implemented in hardware, the performance is affected by the data dependency of the iterative compression function. In this paper, a new functional description is proposed with the aim of achieving higher throughput by mean of reducing the critical path and latency. This description can be used in similar structures of other hash algorithms, such as SHA-1, SHA-2 and RIPEMD-160, which have comparable data dependence. The proposed MD5 hardware architecture achieves a high throughput/area ratio, results of implementation in an FPGA are presented and discussed, as well as comparisons against related works.

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