Introduction

Electrooculography (EOG) is a biomedical signal like Electrocardiogram (ECG), Electroencephalogram (EEG), and Electromyography (EMG) that can be measured and monitored. It’s a method for calculating the “cornea-retinal standing potential”, or the difference between the front and back of the eyeball. The EOG signal shows how much electricity is made when the eyes move. These measurements are used to study how the eyes move and other things that are connected1. This signal has an intensity of between 5 and 20 uV/degree and a frequency of between 5 and 30 Hz2. The “EOG signal” can be used to study saccades, fixational movements, and vergence, among other eye movements. It can tell if someone has degenerative myopia, problems with the retina, or epileptic nystagmus. The “EOG signal” is used for drowsiness detection, “Human Machine Interface (HMI)”, and “eye-tracking” for “biomedical engineering applications”. The “EOG signal” is used to examine various people’s everyday activities3. For EOG signals, several noise suppression algorithms have been established; among them, the bandpass FIR filter offers the greatest accuracy and processing speed4,5,6. Many biological and control device applications employ the EOG signal3,7. In today’s biomedical applications, Human-Computer Interface (HCI) technologies play a vital part in patient communication. As they communicate with vertical “eye movements and blinking”, the “EOG signal” may be employed efficiently for locking-in syndrome patients8. To assess the innovation and superiority of the Radix-2r multiplier-based architecture for denoising EOG (Electrooculography) signals in contrast to cutting-edge designs, various aspects of the proposed design and its theoretical foundations must be investigated. Signal is also utilised to identify diseases like vertigo and dizziness9. In digital signal processing (DSP) designs10, adders and multipliers are key building components. A few experts are working on creating a “multiplier-less fir filter” for “real-time EOG” data11,12. The solutions in11,12 are based on high-throughput distributed arithmetic and variable shifter approaches13. proposes an “area-efficient de-noise filter” for denoising the EOG signal. As a result, a digit recording algorithm like Radix-2r is particularly good at reducing the complexity and “critical path delay” in the multiplication of existing and conventional approaches14. Deep-learning and machine algorithms are very useful for eye movement detection and classification of HCI applications15,16,17,18. Several methods for detecting eye movement in EOG signals have been proposed in the literature throughout the years. Existing electrooculography systems rely solely on software simulations such as MATLAB simulations or other programming languages such as “C, C + +, and Python”. A redesigned FIR filter architecture is developed in hardware in this proposed work. The “low-latency” and “low-power” hardware implementations are required for real-time signal processing applications. Because Moore’s law is slowing, technology alone will not be adequate to supply the computation demand. To solve this difficulty, researchers are focusing on efficient algorithms and domain-specific hardware designs. For biomedical signals, filtering is the first step. Because noise and signal share the same bandwidth, it’s difficult to reduce noise on EOG signals. The existing hardware architectures occupy more area and slow speed. The existing architectures for denoising EOG signals are a Sum Power of Two (SOPOT) based filter12 and a Differential Evolution (DE) algorithm-based filter13. The disadvantages of current architectures overcome the proposed architecture. The computation blocks in the FIR filter consist of a multiplier and an adder. For the multiplication of FIR filter coefficients, a Radix-2r based multiplier is utilised in this study. The “partial products” are generated by the Radix-2r multiplier, and these “partial products” are added using a 4:2 compressor rather than ripple carry adders (RCA). The Radix-2r multiplier is a programmable multiplier like a lookup-table(LUT) based multiplier. The advantage of programmable multipliers is that whenever the filter coefficients have been modified, there is no need to change the entire hardware architecture. Only change partial products generation block, and the benefit is critical path delay is same. But in the case of existing architectures, combinational path delay is changed. This advantage is the key difference between the proposed and current architecture. The advantage of the proposed architecture leads to a reduction in delay and energy. Finally, the proposed FIR filter architecture is compared to research papers that have recently been published.

Here are some potential points of comparison and discussion.

  1. (a)

    Computational Efficiency: The Radix-2r multiplier-based architecture may be more efficient than other architectures in terms of computational efficiency. This efficiency may be ascribed to improved multiplication and addition algorithms, which result in faster processing of EOG signals. The authors could provide detailed comparisons of computational complexity, stressing the advantages of their approach.

  2. (b)

    Resource Utilization: Understanding how different designs use resources is crucial, especially for practical implementation in embedded systems or specialized hardware. The authors could demonstrate how their Radix-2r multiplier-based architecture uses resources more efficiently, resulting in lower power consumption or a smaller hardware footprint than alternatives.

  3. (c)

    Noise Reduction Performance: To assess the proposed design’s superiority, a detailed comparison of noise reduction performance is required. The authors should provide empirical evidence that their architecture outperforms existing methods for denoising EOG signals. This could incorporate quantitative metrics such as increased signal-to-noise ratio (SNR) or qualitative assessments based on visual inspection of denoised signals.

  4. (d)

    Adaptability and Flexibility: It is vital to examine the suggested architecture’s adaptability and flexibility, particularly if it offers advantages in dealing with diverse signal characteristics or responding to different denoising needs. The authors may explain how their design allows for multiple filter combinations or responds to dynamic signal circumstances, making it more practical for real-world applications.

  5. (e)

    Theoretical Foundations: Demonstrating the proposed architecture’s originality requires a more in-depth theoretical knowledge of why it performs better. This could involve describing the mathematical principles that support design decisions, such as the usage of Radix-2r multipliers for efficient signal processing or the theoretical foundation for improving denoising performance in EOG signals.

The following are the article’s main contributions:

  • Reconfigurable Radix-2r Multiplication Implementing adaptable Radix-2r multiplication constants, with r = 3, to dynamically modify FIR filter coefficients, reducing partial products and increasing flexibility.

  • Enhanced Adder-Based Architecture: Traditional multipliers are substituted with optimized compressors (4:2 and 3:2 compressors) and shifters in the RFIR filter design, decreasing the number of required arithmetic units and thus reducing area and resource consumption.

  • Real-time power and Delay optimization Developing a dynamic configuration approach that allows real-time adjustment of filter coefficients, resulting in substantial decreases in power usage and processing delays during adaptive filtering operations.

The present research is divided into seven sections. Section 2 covers the literature survey, while Sect. 3 discusses the “transposed FIR filter” and filter coefficients. Section 4 presents the proposed “FIR filter architecture” and “Radix-2r multiplier” representation. Sections 5 and 6 discuss the simulation and synthesis results of the proposed and existing architectures, followed by the conclusion in Sect. 7.

Literature survey

Digital filters play a critical role in numerous signal processing applications, providing a means to enhance or extract desired information from signals while minimizing undesirable noise or distortion. By transforming an input sequence, they produce an output sequence with improved characteristics, such as reduced noise or interference. Typically comprised of three core elements—adders, multipliers, and delays—digital filters execute numerical calculations on sampled signal values, enabling manipulation of past and future data points within the sequence. Multipliers are essential components in FIR filters, leading to significant resource and power consumption. When coefficients are fixed, FIR filters can be effectively implemented without multipliers by using shift-add operations. However, in scenarios where filter coefficients must be reconfigurable, multiplier-less techniques are not directly applicable. One method to address this involves altering the nonzero digits in the canonical signed digit (CSD)19 representations of the coefficients to adjust the filter’s impulse response. Nonetheless, the number of nonzero bits allowed in CSD representations is limited due to complexity constraints, which, in turn, restricts the reconfigurability of the filters. The binary common subexpression elimination (BCSE) technique is explored in20 for multiplexer-based reconfigurable FIR (RFIR); however, the relationship between the coefficients and control signals is not fully leveraged, leading to unnecessary use of MUXs and sign-correction blocks.

An alternative solution is the Distributed Arithmetic (DA)21 technique, which leverages look-up tables (LUTs) to perform the inner-product operation. In this approach, filter coefficients can be modified by updating the precomputed values stored in the LUTs. DA-based techniques are particularly efficient for fixed-coefficient filters and low-order RFIR filters, owing to the simplicity and efficiency of LUT-based arithmetic. However, the size of the required LUTs increases exponentially with the filter order, resulting in greater area overhead and making coefficient updates more challenging. Additionally, DA-based FIR filters can be power- and time-intensive, especially for high-order filters, which can compromise overall efficiency. Recent AM designs using modified Wallace tree multipliers and inexact 4:2 compressors improved trade-offs between design and error parameters22, but further optimization is possible. Advanced designs using modified Karatsuba algorithms and recursive rounding methods enhanced performance23,24 yet still faced challenges with accuracy and high area utilization.

The existing architectures for denoising EOG signals include the Sum Power of Two (SOPOT) based filter12 and the Differential Evolution (DE) algorithm-based filter13. The proposed architecture addresses the shortcomings of these current designs. In the FIR filter, the computation blocks consist of a multiplier and an adder. This study utilizes a Radix-2r-based multiplier for multiplying FIR filter coefficients. The Radix-2r multiplier generates “partial products,” which are then summed using a 4:2 compressor instead of ripple carry adders (RCA). The Radix-2r multiplier functions as a programmable multiplier, similar to a lookup-table (LUT) )-based multiplier. A key advantage of programmable multipliers is that when filter coefficients are modified, there is no need to alter the entire hardware architecture; only the partial products generation block needs to be adjusted, ensuring the critical path delay remains unchanged. In contrast, existing architectures experience changes in combinational path delay. This advantage is the main distinction between the proposed and current architectures, leading to a reduction in both delay and energy consumption.

FIR filter

The equation of the FIR filter is shown in Eq. 1.

$$y\left(n\right)=\sum_{k=0}^{N-1}h\left(k\right).x\left(n-k\right)$$
(1.)

Filter input and output are represented by x(n − k) and y(n), respectively, in Eq. 1. The coefficients are written as h(k), with the filter’s order being N. In comparison to the direct form, the FIR filter’s transpose form has a higher speed. FIR filter of a transposed form is shown in Fig. 1. The FIR filter used to de-noise the EOG signal has an order of 23 and a pass band frequency of 5–30 Hz25. Table 1 displays the filter coefficients.

Table 1 Coefficients of filtering.
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Fig. 1
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Structure of FIR filter in transposed form.

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A sampling frequency of 250 Hz is used in the EOG signal. The frequency of the pass band is 0.04 rad, while the frequency of the stop band is 0.24 rad. The stopband ripple is 40 dB, whereas the passband ripple is 0.2 dB. Figure 2 depicts the magnitude response of an FIR filter to an EOG signal.

Fig. 2
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FIR filter magnitude response for denoising EOG signals.

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Proposed FIR filter architecture using Radix-2r multiplier

The fixed multiplication technique based on Radix − 2r is adapted from14 and26. N-bit filter coefficient hk may be expressed in Radix − 2r as

$${h}_{k}=\sum_{j=0}^{(N+1)/(r-1)}\left[{h}_{rj-1}+{2}^{0}{h}_{rj}+{2}^{1}{h}_{rh+1}+ \dots+{2}^{r-2}{h}_{rj+r-2}-{2}^{r-1}{h}_{rj+r-1}\right]{2}^{rj}$$
(2.)
$${h}_{k}=\sum_{j=0}^{\raisebox{1ex}{$(N+1)$}\!\left/\!\raisebox{-1ex}{$(r-1)$}\right.}{P}_{j}.{2}^{rj}$$
(3.)

where Pj represents (N + 1)/r − 1 number of pieces each of r + 1 number of bits obtained from N-bit constant hk and Pj also represents as [hrj-1 + 20hrj+21hrj+1+…+2r − 2hrj+2-2r − 1hrj+r−1]. Consider coefficient h1 = 111,111,011,000b in two’s complement representation with N = 12 and r = 3.

$${h}_{1}=\sum_{j=0}^{3}{P}_{j}.{2}^{3j}$$
(4.)
$${h}_{1}={P}_{0}{2}^{0}+{P}_{1}{2}^{3}+{P}_{2}{2}^{6}+{P}_{3}{2}^{9}$$
(5.)

Encoding of Pj is obtained from coefficient h1 is shown in Fig. 3, and the resultant equation is as follows,

$$\begin{aligned}{h}_{1}x&=x\left({P}_{0}{2}^{0}\right)+x{(P}_{1}{2}^{3})+x{(P}_{2}{2}^{6})+x\left({P}_{3}{2}^{9}\right) \\ {h}_{1}x&=x\left(\right(0\left){2}^{0}\right)+x\left(\right(3\left){2}^{3}\right)+x\left(\right(-1\left){2}^{6}\right)+x\left(\right(0\left){2}^{9}\right) \\ {h}_{1}x&=\left(x\ll3\right)+\left(x\ll4\right)-\left(x\ll6\right) \end{aligned}$$
(6.)

Similarly, the remaining coefficients are shown in Table 2. The proposed filter architecture is shown in Fig. 4. The Radix-2r multiplier block generates partial products, which are PP0, PP1, PP2, and PP3. From Table 2, we can easily identify the multiplier’s critical path delay as coefficient h8.

Table 2 Radix-2r encoded representation for filter coefficients.
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Fig. 3
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Encoding of h1 to Pj.

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Fig. 4
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Proposed FIR filter.

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The critical path delay of conventional structure27 is T = 25∗XOR/XNOR + NOR + 21 ∗ AND + NAND + 16 ∗ OR + RCA. The block schematic of the existing structure28 is shown in Fig. 5. The critical path delay of the existing structure is T = 3 ∗ RCAs. Where RCA is a ripple carry adder. The block schematic of the proposed structure is shown in Fig. 6.

Fig. 5
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Block schematic of existing structure28.

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Fig. 6
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Block schematic of the proposed structure.

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The proposed structure uses 3: 2 and 4: 2 compressors instead of RCAs. The compressor structures are taken from29. The final RCA is required to add the final S (sum) and C (carry) outputs. The critical path delay of the proposed structure is T = 2 ∗ XOR + 3 ∗ MUX + RCA. The functionality of the proposed structure is explained with an example using an input sample of 16-bit hexadecimal (h) and its equivalent decimal (d) values. The example of the proposed structure for filter coefficient h8 is shown in Fig. 7.

Fig. 7
figure 7

Example of the proposed structure for filter coefficient h8.

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Where, X = Input sample; h8 = Filter Coefficient; P P0, P P1, P P2, P P3 = Partial Products; {P P0 = X < < 3, P P1 = −(X < < 6), P P2 = −(X < < 7), P P3 = (X < < 9)}; S8, S = Sum′ s of Compressors; C8, C = Carry′ s of Compressors; Y1 = Output of the previous stage; Y2 = Input to next stage.

Consider that the input sample X and output of previous stage Y1 values are assumed as 227d (E3h ) and 34281d (85E9h), respectively. From Table 1, the filter coefficient h8 is 328d (148h). Based on Table 2, the first partial product (PP0) becomes 1816d (718h), the second partial product (PP1) becomes − 14,528d (FC740h), the third partial product (PP2) becomes − 29,056d (F8E80h) and the fourth partial product (P P3) becomes 116,224d (1C600h). These partial products are given as inputs to the 4 2 compressor. The outputs generated by the 4: 2 compressor are Sum(S8) − 96,552d (FE86D8h) and Carry(C8) 85,504d (14E00h). The inputs of the 3: 2 compressor are S8, C8 (left shift by 1-bit) and the output of the previous stage Y1. The outputs generated by the 3: 2 compressor are Sum(S) − 221391d (F C9F31h) and Carry(C) 165064d (284C8h), which is added through the final adder as shown in Fig. 7. The inputs of the final adder are S and C(left shift by 1-bit). The output of the final adder is Y2 = 108,737d (1A8C1h). The actual value is obtained by using Y2 = X ∗ h8 + Y1 = 227 ∗ 328 + 34,281 = 108,737 and the output of proposed structure value is 108,737d.

Advantages

Reduced Hardware Requirements: The RADIX-2r algorithm minimises the number of adders, which leads to lower power consumption and smaller silicon area, making it suitable for energy-efficient hardware designs.

Efficiency in Power and Area: By minimising the number of adders required, the algorithm not only lowers power consumption but also reduces the overall area, making it ideal for resource-constrained applications.

Disadvantages

Increased Design Complexity: Implementing the RADIX-2r algorithm can be more challenging due to its sophisticated structure, requiring more effort in the design and verification stages.

Less Advantageous for Low-Order Filters: The algorithm may not offer substantial benefits for low-order FIR filters, where simpler techniques might perform just as well or better.

Limitations

Restricted Use Case: The RADIX-2r algorithm is primarily optimized for FIR filters, limiting its effectiveness in other digital signal processing applications where different optimizations may be needed.

Performance Dependence on Filter Complexity: The algorithm’s performance gains are most evident in high-order filters with many coefficients, making it less effective in scenarios with simpler filter designs.

Simulation results

The implementation of a denoising filter using Verilog HDL is based on a Radix-2r multiplier with a compressor. This filter is designed to process 16-bit data input from a standard EOG database30. The purpose of this filter is to reduce noise in the EOG signal and provide a clean, denoised output. The entire process involves several steps, including compilation using Intel Quartus software and simulation in Modelsim. The input to the HDL filter block is the raw, noisy “EOG signal” obtained from the EOG database. The filter block itself is designed to operate on this input data using a clock input to synchronize its processing. After processing, the output is a 16-bit denoised EOG signal.

The performance of the denoising filter is assessed using two key metrics: Mean Square Error (MSE) and Signal-to-Noise Ratio (SNR). These metrics are crucial for evaluating the filter’s effectiveness in reducing noise. The obtained MSE of 0.6246 reflects the average squared difference between the noisy and denoised EOG signals, with lower values indicating better denoising performance. The SNR of 27.21 dB demonstrates a significant enhancement in signal quality, as higher SNR values denote less noise in the denoised signal. When comparing the proposed architecture with references31,32,33, it is observed that references32,33 achieve SNR and MSE values similar to those of the proposed design. However, reference31 does not achieve comparable results, indicating that the proposed architecture outperforms reference31 in terms of both SNR and MSE.

.

The benefits of the Radix-2r multiplier with a compressor-based FIR filter are evident in the waveform results shown in Figs. 8, 9, 10, 11, 12 and 13. These figures display the noisy and denoised EOG signals for both horizontal and vertical components. It is apparent that the filter successfully reduces the noise present in the raw EOG signals, resulting in cleaner and more accurate data. Overall, the successful implementation of the denoising filter demonstrates its effectiveness in processing noisy EOG signals, enhancing the quality and accuracy of the data. The usage of Verilog HDL and the Radix-2r multiplier with a compressor allows for efficient hardware implementation, while the Intel Quartus software facilitates the smooth compilation of the HDL filter block. The Modelsim simulator is instrumental in verifying the functionality and performance of the filter.

Fig. 8
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Noisy EOG signal and denoised horizontal EOG signal.

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Fig. 9
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Test Case − 1 noisy EOG signal and denoised horizontal EOG signal.

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Fig. 10
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Test Case − 2 noisy EOG signal and denoised horizontal EOG signal.

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Fig. 11
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Noisy EOG signal and denoised vertical EOG signal.

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Fig. 12
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Test Case − 3 noisy EOG signal and denoised vertical EOG signal.

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Fig. 13
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Test Case − 4 noisy EOG signal and denoised vertical EOG signal.

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The Intel DSP Builder tool was utilized to verify the functionality of the proposed design, employing the functional verification setup depicted in Fig. 14. “Intel DSP Builder” is a software application that seamlessly integrates “MATLAB and Simulink with Intel’s Quartus”. This powerful tool offers various functionalities, including automatic development of Verilog HDL test benches and control over Quartus compilation. Leveraging “fixed-point arithmetic”, “logical operators”, and the Simulink environment, “Intel DSP development boards” facilitate rapid prototyping. The “SignalTap II Logic Analyzer” effectively captures signals from “Intel devices” on the “DSP board”, while the resulting data can be imported into the MATLAB workspace for evaluation.

Fig. 14
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Functional verification setup using Intel DSP builder.

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Through rigorous simulation testing, using different test cases within Intel DSP Builder, the design’s performance was thoroughly evaluated, and the results are illustrated in Figs. 15, 16, 17, 18, 19 and 20. This verification process assures the design’s accuracy, efficiency, and compliance with the desired specifications. By leveraging Intel DSP Builder’s capabilities, potential issues were identified and addressed early in the development phase, leading to a robust and optimized solution. The simulation results demonstrate the design’s proficiency in handling diverse input scenarios, confirming its suitability for real-world signal processing applications. Overall, the successful verification underscores the design’s reliability, enabling its seamless integration and deployment in practical applications.

Fig. 15
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Simulation results of proposed design using Intel DSP builder Test Case 1.

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Fig. 16
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Simulation results of proposed design using Intel DSP builder Test Case 2.

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Fig. 17
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Simulation results of proposed design using Intel DSP builder Test Case 3.

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Fig. 18
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Simulation results of proposed design using Intel DSP builder Test Case 4.

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Fig. 19
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Simulation results of proposed design using Intel DSP builder Test Case 5.

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Fig. 20
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Simulation results of proposed design using Intel DSP builder Test Case 5.

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Synthesis results

The synthesized results of the Radix-2r multiplier with a 4:2 compressor-based FIR filter are compared in terms of hardware resources utilised (Like “Area, Power, Delay, Area Delay Product (ADP) and Energy per Sample (EPS)”34,35,36, for understanding design improvement with the filter implemented using “sum of power of two (SOPOT)”12, conventional design27, differential evolution algorithm based filter (DE)13 and Radix-2r multiplier with ripple carry adder28. All filters are implemented using on same platform of gate-level Verilog HDLand up to filter order 24. Theoretical Gate count and critical path delay of the proposed design and existing are shown in Table 3. The ASIC synthesis results of the proposed design and existing are tabulated in Table 4. The percentage gain of Area, power, and delay are tabulated in Table 5, and the Area delay product and Energy per sample (EPS) are shown in Table 6. The “Conventional FIR filter” results shown in Table 4 use a “radix-8 multiplier for coefficient multiplication”. In SOPOT-based filter12, a “variable shifter” circuit is used for “coefficient multiplication”. The throughput of the “shifter circuit” in12 is based on the sign power of two terms present in a coefficient. In Table 4 Differential Evolution algorithm-based filter13 is the “CSD-based shift and add implementation for coefficient multiplication”. In Table 4 Radix-2r multiplier with ripple carry adder-based filter28 is the “CSD-based shift and add implementation for coefficient multiplication”. The theoretical Gate count and critical path delay are shown in Table 3. It indicates that the conventional design takes 63 full adders, DE takes 21 adders, Radix-2r take 16 adders, and the proposed design takes 12* 4:2 compressor + 11 * 3:2 compressor. The conventional design critical path delay is 19*Full Adder + 2*NOT gate + XOR gate + Adder, and the proposed design critical path delay is 4:2 compressor + 3:2 compressor + Adder. The proposed filter shown in Table 4 uses a Radix-2r multiplier with a compressor for coefficient multiplication. The “ASIC synthesis results are obtained using Cadence RTL compiler for UMC 90nm technology”. The performance metrics for the implemented filter are taken as power, area and delay. The proposed and existing filter performance is measured in terms of “area, power, delay”, ADP and EPS. The proposed filter architecture carries out a 71.48% reduction in area, a 73.28% reduction in power, a 51.84% reduction in delay, an 86.22% reduction in ADP and a 92.38% reduction in EPS as compared to the SOPOT filter12. The proposed filter architecture carries out a 33.46% reduction in delay as compared to28. The area delay product and power delay product of the proposed architecture are 29% and 30% reduction as compared to28. The estimated delay values are shown in the bar chart of Fig. 21 for comparison. As shown in Figs. 22 and 23, the proposed FIR filter architecture has lesser Area, power, delay, ADP and EPS when compared to that of a conventional27 filter implemented using the sum of power of two (SOPOT)12, Differential Evolution algorithm based filter(DE)13 and Radix-2r multiplier with ripple carry adder28. After a detailed study, we found that the proposed design is better than all existing designs.

Table 3 Theoretical gate count and critical path delay.
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Table 4 Synthesis results of proposed FIR filter.
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Table 5 Percentage reduction of hardware resources in the proposed FIR filter in comparison to the existing filter.
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Table 6 Percentage reduction of ADP and EPS in the proposed FIR filter in comparison to the existing filter.
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Fig. 21
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Delay values of proposed FIR filter architecture compared with that of existing architectures.

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Fig. 22
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Graphical representation of percentage reduction “Area, power and Delay” values of proposed “FIR filter architecture” compared with that of existing architectures.

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Fig. 23
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Graphical representation of percentage reduction ADP and EPS values of proposed “FIR filter architecture” compared with that of existing architectures.

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The comparison of the proposed architecture with references31,32,33 reveals notable differences in area and power consumption. Specifically, the excess area for these references is as follows: reference31 shows an excess area of 93.40% compared to the proposed architecture, reference32 shows an excess area of 94.72%, and reference33 shows a substantial excess area of 116.26%. Regarding power consumption, reference31 exhibits an excess power of 20.36% relative to the proposed architecture. In contrast, reference32 demonstrates a significantly higher excess power of 182.43%, and reference33 shows an even greater excess power of 210.62%. These figures highlight the efficiency advantages of the proposed architecture in terms of both area and power consumption.

Conclusion and future work

In this research work, a “modified FIR filter” is proposed for denoising of “EOG signal”. The proposed Radix-2r multiplier with compressor-based FIR filter is implemented to denoise the real EOG signal. The ModelSim-Altera 10.1b is used to verify the functionality of the proposed filter architecture. The proposed and existing filter “performance is measured in terms of area, power, and delay”. The SOPOT-based filter architecture carries out a 3.26% reduction in delay compared to the “conventional filter”. The “DE algorithm-based filter architecture” carries out a 20.57% reduction in delay as compared to the “conventional filter”. The “Radix-2r multiplier” with ripple carry adder-based filter architecture carries out a 29.70% reduction in delay compared to the “conventional filter”. The proposed filter architecture carries out a 53.23% reduction in delay as compared to the content filter. The proposed architecture’s area delay product and power delay products are 29% and 30% reduction compared to the Radix-2r multiplier with ripple carry adder-based filter architecture. The proposed FIR filter architecture is very useful for high-speed biomedical applications. Here presented filter efficiently removes the noise in the raw EOG signal. In future research work, deep learning-based methods are developed for detecting eye movements using a de-noised EOG signal. In addition, denoising EOG signal can be performed using wavelet transform architectures and developing a VLSI-based Electrooculography diagnostic system for epileptic disease identification.