Abstract
A new neural network-based fault classification strategy for hard multiple faults in analog circuits is proposed. The magnitude of the harmonics of the Fourier components of the circuit response at different test nodes due to a sinusoidal input signal are first measured or simulated. A selection criterion for determining the best components that describe the circuit behaviour under fault-free (nominal) and fault situations is presented. An algorithm that estimates the overlap between different faults in the measurement space is also introduced. The learning vector quantization neural network is then effectively trained to classify circuit faults. Performance measures reveal very high classification accuracy in both training and testing stages. Two different examples, which demonstrate the proposed strategy, are described.
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J.W. Bandler and A.E. Salama, “Fault Diagnosis of Analog Circuits,” Proc. IEEE, Vol. 73, pp. 1279–1325, 1985.
M.A. El-Gamal, “Fault Location and Parameter Identification in Analog Circuits,” Ph.D. Dissertation, Ohio University, Athens, Ohio, 1990.
P. Dague, O. Jehl, P. Deves, P. Luciani, and P. Taillibert, “When Oscillators Stop Oscillating,” Proc. 12th Int. Joint Conf. on Artificial Intelligence, 1991, Sydney, Australia, pp. 1109–1115.
A. Fanni, P. Diana, A. Giua, and M. Perezzani, “Qualitative Dynamic Diagnosis of Circuits,” Artificial Intelligence for Engineering Design, Analysis and Manufacturing, Vol. 7, pp. 53–64, 1993.
F. Pipitone, K. Dejong, and W. Spears, “An Artificial Intelligence Approach to Analog System Diagnosis,” Testing and Diagnosis of Analog Circuits and Systems, R. Liu (Ed.), Van Nostrand Reinhold, 1991, pp. 1517–1521.
J.A. Starzyk and M.A. El-Gamal, “Artificial Neural Network for Testing Analog Circuits,” Proc. IEEE Int. Symp. Circuit and Systems, New Orleans, Louisiana, 1990, Vol. 3, pp. 1851–1854.
G. Rutkowski, “A Neural Approach to Fault Location in Nonlinear DC Circuits,” Proc. Int. Conf. on Artificial Neural Networks, Brighton, 1992, pp. 1123–1126.
A. Fanni, A. Giua, and E. Sandoli, “Neural Networks for Multiple Fault Diagnosis in Analog Circuits,” Neural Networks Theory, Technology and Applications, IEEE Technology Update Series, 1996, pp. 745–752.
C. Parten, R. Saeks, and R. Pap, “Fault Diagnosis and Neural Networks,” Proc. IEEE Int. Conference on Systems, Man and Cybernetics, Charlottesville, Virginia, 1991, pp. 1517–1521.
M.A. El-Gamal, “A Knowledge-Based Approach for Fault Detection and Isolation in Analog Circuits,” Proc. IEEE Int. Conference on Neural Networks, Houston, Texas, Vol. 3, 1997, pp. 1580–1584.
M.A. El-Gamal and A.Z. Ghalwash, “A Neuro-Expert System Architecture for Analog Fault Diagnosis,” Proc. Int. ICSC Symp. on Engineering of Intelligent Systems, Vol. 2, Tenerife, Spain, 1998, pp. 227–233.
S. Yu, B. Jervis, K. Eckersall, I. Bell, A. Hall, and G. Taylor, “Neural Network Approach to Fault Diagnosis in CMOS Opamps with Gate Oxide Short Faults,” Electron. Lett., Vol. 30, pp. 695–696, 1994.
Y. Maidon, B. Jervis, N. Dutton, and S. Lesage, “Diagnosis of Multifaults in Analog Circuits Using Multilayer Perceptrons,” IEE Proc. Circuits Devices Syst., Vol. 144, pp. 149–154, 1997.
J. Meador, A. Wu, C. Tseng, and T. Lin, “Fast Diagnosis of Integrated Circuit Faults Using Feedforward Neural Networks,” Proc. Int. Joint Conference on Neural Networks, Seatle, Washington, 1991, pp. 269–273.
G. Stenbakken and T. Souders, “Developing Linear Error Models for Analog Devices,” IEEE Trans. Instrumentation and Measurements, Vol. 43, pp. 157–163, 1994.
M.A. El-Gamal, A.S. Hassan, and H.L. Abdel-Malek, “A New Approach for the Selection of Test Points for Fault Diagnosis,” Proc. IEEE Int. Symp. on Circuits and Systems, Seattle, Washington, USA, Vol. 3, 1995, pp. 2019–2022.
V. Prasad and S. Pinjala, “Boolean Method for Selection of Minimal Set of Test Nodes for Analogue Fault Dictionary,” Electron. Lett., Vol. 29, pp. 747–749, 1993.
T. Kohonen, “The Self-Organizing Map,” Proc. of IEEE,Vol. 78, pp. 1464–1480, 1990.
W. Becraft and P. Lee, “An Integrated Neural Network/Expert System Approach for Fault Diagnosis,” Computers in Chemical Engineering, Vol. 17, pp. 1001–1014, 1993.
B. Apstein, M. Czigler, and S. Miller, “Fault Detection and Classification in Linear Integrated Circuits: An Application of Discrimination Analysis and Hypothesis Testing,” IEEE Trans. Computer-Aided Design, Vol. 12, pp. 102–113, 1993.
Pspice, Circuit Analysis User' Guide, The MicroSim Corp., CA, USA, 1992.
D. Pa and A. Hatzopoulos, “Supply Current Testing in Linear Bipolar Ics,” Electron. Lett., Vol. 30, pp. 128–130, 1994.
V. Prasad and N. Babu, “On Minimal Set of Test Nodes for Fault Dictionary of Analog Circuit Fault Diagnosis,” Journal of Electronic Testing: Theory and Applications, Vol. 7, pp. 255–258, 1995.
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El-Gamal, M., El-Yazeed, M.A. A Combined Clustering and Neural Network Approach for Analog Multiple Hard Fault Classification. Journal of Electronic Testing 14, 207–217 (1999). https://doi.org/10.1023/A:1008353901973
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DOI: https://doi.org/10.1023/A:1008353901973