Abstract
A processor simulator is an essential tool for developing, testing, and verifying flight software in the space domain; this tool should be capable of correctly simulating a space-grade processor with high performance and cycle-accuracy. Existing space simulators typically use single-thread-based interpretation methods to satisfy these requirements. Since these methods involve sequential core execution by a single thread, which degrades the overall performance and cycle-accuracy, they are unsuitable for multi-core processor simulations. In this study, we propose a cycle-accurate and high-performance multi-core processor simulator based on multi-threading called the Scalable Processor Architecture multi-core multi-threading simulator (S2MSim) which accurately models the working of the GR740 quad-core processor through three schemes. First, we assigned each GR740 core to a host thread to improve the performance and dynamically allocated a simulator manager to these specific host threads to minimize the overhead induced by thread communications. Second, we analyzed the inter-core interference effects and reflected the results required for each core to achieve a high cycle-accuracy. Finally, we used a fine-grained lock to provide the simulated cores with simultaneous access to shared resources and spin-lock to thread synchronization. The experimental results showed that on an average, the S2MSim could run 3.09 and 4.18 times faster than TSIM3-LEON4 and laysim-gr740, respectively. We achieved a high cycle-accuracy within a ± 3% error margin compared to that shown by the GR740 development board from Cobham Gaisler AB.
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Jeong, JY., Lee, CH. S2MSim: Cycle-Accurate and High-Performance Simulator Based on Multi-Threading for Space Multi-Core Processor. Int. J. Aeronaut. Space Sci. 24, 1465–1478 (2023). https://doi.org/10.1007/s42405-023-00627-y
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DOI: https://doi.org/10.1007/s42405-023-00627-y