Abstract
Existing zero-knowledge-based intellectual property (IP) watermarking techniques require a third party to identify suspected IP ownership. However, the credibility and controllability of the third party raise a new challenge to watermark detection in field programmable gate array (FPGA) IP cores. In this work, a public verifiable scheme for watermark embedding and blind detection in FPGA IP cores is proposed. The scheme uses the key threshold of interactive zero-knowledge protocol as the blind detection evidence for secure watermark authentication. The identification information of the IP owner and the key detection threshold is public in the zero-knowledge proof protocol. The security of public watermark detection for IP watermark adopts the idea of zero knowledge in cryptography. The scrambling algorithm will be used to scramble the authentication information in FPGA IP cores. In this case, the security of public watermark detection can be guaranteed. Without the original IP circuit and the third party, watermarks in FPGA IP cores can be blindly detected on site. The experiments show that our scheme improves the credibility of the watermarks detected by trading partners in public. The performances in terms of resource overhead, robustness and security are encouraging.
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References
Adelsbach A, Sadeghi AR (2001) Zero-knowledge watermark detection and proof of ownership. Information hiding. Springer, Berlin, pp 273–288
Castillo E, Meyer-Baese U, Garcia A, Parrilla L, Lloris A (2007) Ipp@ hdl: efficient intellectual property protection scheme for IP cores. IEEE Trans Very Large Scale Integr VLSI Syst 15:578–591
Chang CH, Cui A (2010) Synthesis-for-testability watermarking for field authentication of VLSI intellectual property. IEEE Trans Circuits Syst I Regul Pap 57:1618–1630
Chang CH, Zhang L (2014) A blind dynamic fingerprinting technique for sequential circuit intellectual property protection. IEEE Trans Comput Aided Des Integr Circuits Syst 33:76–89
Cramer R, Damgard I (2014) On the amortized complexity of zero-knowledge protocols. J Cryptol 27:284–316
Craver S, Memon N, Yeo BL, Yeung MM (1998) Resolving rightful ownerships with invisible watermarking techniques: limitations, attacks, and implications. IEEE J Sel Areas Commun 16:573–586
Cui A, Chang CH (2008) Intellectual property authentication by watermarking scan chain in design-for-testability ow. In: IEEE International Symposium on Circuits and Systems. IEEE, pp 2645–2648
Cui A, Chang CH, Tahar S (2008) IP watermarking using incremental technology mapping at logic synthesis level. IEEE Trans Comput Aided Des Integr Circuits Syst 27:1565–1570
Cui A, Chang CH, Tahar S, Abdel-Hamid AT (2011) A robust FSM watermarking scheme for IP protection of sequential circuit design. IEEE Trans Comput Aided Des Integr Circuits Syst 30:678–690
He YZ, Wu CK, Feng DG (2005) Publicly verifiable zero-knowledge watermark detection. Ruan Jian Xue Bao (J Softw) 16:1606–1616
Lach J, Mangione-Smith WH, Potkonjak M (2001) Fingerprinting techniques for field-programmable gate array intellectual property protection. IEEE Trans Comput Aided Des Integr Circuits Syst 20:1253–1261
Le-Gal B, Bossuet L (2012) Automatic low-cost IP watermarking technique based on output mark insertions. Design Autom Embed Syst 16:71–92
Li D, Zheng W, Zhang M (2007) Advancement on IP watermarking techniques. J Circuits Syst 4:85–92
Liang W, Sun X, Ruan ZQ, Long J (2011a) A sequential circuit-based IP watermarking algorithm for multiple scan chains in design-for-test. Radioengineering 20(2):533–538
Liang W, Sun X, Xia Z, Sun D, Long J (2011b) A chaotic IP watermarking in physical layout level based on FPGA. Radioengineering 20:118–125
Liang W, Wu K, Xie Y, Duan J (2015) TDCM: an IP watermarking algorithm based on two dimensional chaotic mapping. Comput Sci Inf Syst 12(2):823–841
Meenakumari M, Athisha G (2013) A survey on protection of FPGA based IP designs. Int J Adv Electr Electr Eng 2:93–99
Nie T, Liu H, Zhou L (2012) FPGA IP protection and detection techniques. Semicond Technol 8:585–607
Nie T, Li Y, Zhou L, Toyonaga M (2013) A multilevel fingerprinting method for FPGA IP protection. In: 2013 IEEE International Symposium on Circuits and Systems (ISCAS), pp 1789–1792
Opencores (2015) http://www.open-cores.org
Qu G (2001) Publicly detectable techniques for the protection virtual components. In: Proceedings of the 38th annual Design Automation Conference. ACM, pp 474–479
Qu G (2002) Publicly detectable watermarking for intellectual property authentication in VLSI design. IEEE Trans Comput Aided Des Integr Circuits Syst 21:1363–1368
Saha D, Sur-Kolay S (2010) A unified approach for IP protection across design phases in a packaged chip. In: 23rd International Conference on VLSI Design. IEEE, pp 105–110
Saha D, Sur-Kolay S (2012) Secure public verification of IP marks in FPGA design through a zero-knowledge protocol. IEEE Trans Very Large Scale Integr VLSI Syst 20:1749–1757
Shivasankar K, Nehru AB (2013) A strong FSM watermarking propose for IP security of sequential circuit design. Int J New Trends Electr Commun 1:24–30
Virtex-II Pro and Virtex-II Pro X Platform FPGAs (2014) Complete data sheet. http://www.xilinx.com/support/documentation/data_sheets/ds083.pdf
Xie X, Qiu S (2005) Current status and development of IP in China. Semicond Technol 6:1–4
Zhang L, Chang CH (2012) State encoding watermarking for field authentication of sequential circuit intellectual property. In: 2012 IEEE International Symposium on Circuits and Systems (ISCAS), pp 3013–3016
Zhang J, Lin Y, Che W, Wu Q, Lu Y (2012) Efficient verification of IP watermarks in FPGA designs through lookup table content extracting. IEICE Electr Express 9:1735–1741
Zhang J, Lin Y, Lyu Y, Wang X (2013) A chaotic-based publicly verifiable FPGA IP watermark detection scheme. Sci Sin Inf 43:1096–1110
Acknowledgments
This work is supported by the National Nature Science Foundation of China (Grants 61202462, 61572188, 61502405), Beijing Higher Education Young Elite Teacher Project (YETP0683), Science Foundation of China University of Petroleum (Beijing) (No. 01JB0423), the Scientific Research Fund of Hunan Provincial Education Department (14A047), the Research Project supported by Xiamen University of Technology (YKJ15019R), Xiamen Science and Technology Project (3502Z20133033) and National Health and Family Planning Commission Fund (WKJ-FJ-35).
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Liang, W., Long, J., Chen, X. et al. A new publicly verifiable blind detection scheme for intellectual property protection. Int J Syst Assur Eng Manag 8 (Suppl 3), 2017–2029 (2017). https://doi.org/10.1007/s13198-016-0423-5
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DOI: https://doi.org/10.1007/s13198-016-0423-5