Abstract
With the augmentation in multimedia technology, demand for high-speed real-time image compression system has also increased. JPEG 2000 is the latest generation of static image coding algorithm which builds and improves on its predecessor JPEG. In JPEG 2000, the embedded block coding with optimal truncation is the core of entropy coding algorithm and the most important element to calculate the very hard portion in the compressing process of JPEG 2000 image compression standard. Various applications, such as medical imaging, satellite imagery, digital cinema, and others, require high-speed, high-performance BPC architecture. Hardware requirement of these existing architectures is very high, and throughput is low. To solve this problem, an efficient bit plane coder (BPC) architecture has been proposed in which three coding passes operate in parallel and are allowed to progress independently to scan the four bits of each column in parallel. The entire design of BPC encoder is tested on the field-programmable gate array platform. The implementation results show on the one hand that throughput of the proposed architecture of BPC architecture operates at 434.59 MHz. On the other hand, our design outperforms well-known techniques with respect to the processing time, such that it is capable of encoding one bit plane in 232 clock cycles under any circumstances. It can reach 90% reduction when compared to bit plane sequential. Moreover, it is capable of encoding digital cinema size (2048 × 1080) at 42 frames per second. Therefore, it satisfies the requirement of applications like cartography, medical imaging, satellite imagery, and others, which demand high-speed real-time image compression system.
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References
Marcellin, M.W., Taubman, D.S., JPEG2000: Image Compression Fundamentals, Standards, and Practice, Kluwer International Series in Engineering and Computer Science, Secs 642
Adams, M.D.: The JPEG 2000 Still Image Compression Standard, in ISO/IEC JTC 1/SC 29/WG 1N 2412.2002
Taubman, D.: High performance scalable image compression with EBCOT. IEEE Trans. Image Process. 9(7), 1158–1170 (2000)
Adams, M.D., Kossentini, F.: Jasper: a software-based JPEG-2000 codec implementation. In: Proceedings of the IEEE International Conference on Image Processing, vol. 2, pp. 53–56 (2000)
Dyer, M., Taubman, D., Nooshabadi, S.: Improved throughput arithmetic coder for JPEG 2000. In: IEEE International Conference on Image Processing, pp. 2817–2820 (2004)
Andra, K., Chakrabarti, C., Acharya, T.: A high performance JPEG 2000 architecture. IEEE Trans. Circuits Syst. Video Technol. 13(3), 209–218 (2003)
ISO/IEC JTC1/SC29/WG1/N1646R: JPEG 2000 Part I final committee draft, version 1.0. http://www.jpeg.org/public/fcd15444-1.pdf (2000). Accessed March 2000
Saidani, T., Atri, M., Lekhriji, L., Tourki, R.: An efficient hardware implementation of parallel EBCOT algorithm for JPEG 2000. J. Real-Time Image Process. 11, 1–12 (2013)
ISO/IEC JTC 1/SC 29/WG 1, (ITU–T SG8) Coding of Still Pictures, JBIG (Joint Bilevel Image Experts Group), JBIG Committee, 16 Juillet 1999
Dyer, M., Nooshabadi, S., Taubman, D.: Reduced latency arithmetic decoder for JPEG 2000 block decoding. In: IEEE International Symposium on Circuits and Systems, 2005. ISCAS 2005, vol. 3, pp. 2076–2079, 23–26 May 2005
Modrzyk, D., Staworko, M.: A high-performance architecture of JPEG 2000 encoder. In: 19th European Sinal Processing Conference (EUSIPCO 2011), Barcelona, Spain, 29 August–2 September 2011
Mansouri, A., Ahaitouf, A., Abdi, F.: Fast FPGA implementation of EBCOT block in JPEG 2000 standard. Int. J. Comput. Sci. Issues (IJCSI) 8(5), 551–557 (2011)
Modrzyk, D., Staworko, M.: A high-performance architecture of JPEG 2000 encoder. In: 19th European Signal Processing Conference (EUSIPCO 2011), September 2011
Sarawadekar, K., Banerjee, S.: A high speed bit plane coder for JPEG 2000 and its FPGA implementation. In: 17th European Signal Processing Conference (EUSIPCO 2009), September 2009
Sarawadekar, K., Banerjee, S.: An efficient pass-parallel architecture for embedded block coder in JPEG 2000. In: IEEE Transactions on Circuits and Systems for Video Technology, vol. 21, no. 6, June 2011
Acharya, T., Tsai, P.: JPEG 2000 Standard for Image Compression: Concepts Algorithms and VLSI Architectures. Wiley, Hoboken (2005)
Dyer, M., Nooshabadi, S., Taubman, D.: Design and analysis of system on a chip encoder for JPEG2000. IEEE Trans. Circuits Syst. Video Technol. 19, 215–225 (2009)
Liu, K., Wu, C., Li, Y.: A high-performance VLSI architecture of EBCOT block coding in JPEG2000. J Electron. (China) 23(1), 89–93 (2006)
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Ghodhbani, R., Saidani, T., Horrigue, L. et al. An efficient pass-parallel architecture for embedded block coder in JPEG 2000. J Real-Time Image Proc 16, 1595–1606 (2019). https://doi.org/10.1007/s11554-017-0666-7
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DOI: https://doi.org/10.1007/s11554-017-0666-7