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High performance word level sequential and parallel coding methods and architectures for bit plane coding

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Science in China Series F: Information Sciences Aims and scope Submit manuscript

Abstract

This paper introduced a novel high performance algorithm and VLSI architectures for achieving bit plane coding (BPC) in word level sequential and parallel mode. The proposed BPC algorithm adopts the techniques of coding pass prediction and parallel & pipeline to reduce the number of accessing memory and to increase the ability of concurrently processing of the system, where all the coefficient bits of a code block could be coded by only one scan. A new parallel bit plane architecture (PA) was proposed to achieve word-level sequential coding. Moreover, an efficient high-speed architecture (HA) was presented to achieve multi-word parallel coding. Compared to the state of the art, the proposed PA could reduce the hardware cost more efficiently, though the throughput retains one coefficient coded per clock. While the proposed HA could perform coding for 4 coefficients belonging to a stripe column at one intra-clock cycle, so that coding for an N×N code-block could be completed in approximate N 2/4 intra-clock cycles. Theoretical analysis and experimental results demonstrate that the proposed designs have high throughput rate with good performance in terms of speedup to cost, which can be good alternatives for low power applications.

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References

  1. Boliek M, Christopoulos C, Majani E. JPEG2000 Part I Final Committee Draft Version 1.0, ISO/IEC JTC1/SC29/WG1 N1646R, March 2000

  2. Skadras A, Christopoulos C, Ebrahimi T. The JPEG2000 still image compression standard. IEEE Sig Proc Mag, 2001, 18(5): 36–58

    Article  Google Scholar 

  3. Mallat S G. A theory for multiresolution signal decomposition: the wavelet representation. IEEE Trans Pattern Anal Mach Intelli, 1989, 11(7): 674–693

    Article  MATH  Google Scholar 

  4. Daubechies I, Sweldens W. Factoring wavelet transforms into lifting schemes. J Fourier Anal Appl, 1998, 4: 247–269

    Article  MATH  MathSciNet  Google Scholar 

  5. Gao X, Zhong H. Parameterization of 3-channel non-separable 2-D wavelets and filters. Sci China Ser F-Inf Sci, 2004, 47(3): 362–371

    Article  MATH  MathSciNet  Google Scholar 

  6. Taubman D. High performance scalable image compression with EBCOT. IEEE Trans Image Proc, 2000, 9(7): 1158–1170

    Article  Google Scholar 

  7. Taubman D, Ordentlich E, Weinberger M, et al. Embedded block coding in JPEG2000. Sig Proc: Image Commun, 2002, 17: 47–72

    Google Scholar 

  8. Lian C J, Chen K F, Chen H H, et al. Analysis and architecture design of block-coding engine for EBCOT in JPEG2000. IEEE Trans Circuits Syst Video Tech, 2003, 13: 219–230

    Article  Google Scholar 

  9. Zhu Y, Fu J, Wu Z, et al. A JPEG2000 optimized bit plane scanning method based on multilevel query table. Acta Elec Sin (in Chinese), 2004, 32(5): 810–813

    Google Scholar 

  10. Chiang J S, Lin Y S, Hsieh C Y. Efficient pass parallel architecture for EBCOT in JPEG2000. In: Proceeding of IEEE ISCAS’2002, 2002, 1: 773–776

    Google Scholar 

  11. Chiang J S, Chang C H, Lin Y S, et al. High-speed EBCOT with dual context-modeling coding architecture for JPEG2000. In: Proceeding of IEEE ISCAS’2004, 2004, 3: 865–868

    Google Scholar 

  12. Xu C, Han Y, Zhang Y. Bit-plane and pass dual parallel architecture for coefficient bit modeling in JPEG2000. In: Proceeding of IEEE ICASSP’2004, 2004, 5: 85–88

    Google Scholar 

  13. Fang H C, Wang T C, Chang Y W, et al. Novel word-level algorithm of embedded block coding in JPEG2000. In: Proceeding of IEEE ICME’2003, 2003, 1: 123–139

    Google Scholar 

  14. Fang H C, Chang Y W, Wang T C, et al. Parallel embedded block coding architecture for JPEG 2000. IEEE Trans Circuits Syst Video Tech, 2005, 15(9): 1086–1097

    Article  Google Scholar 

  15. Xiong C Y, Tian J W, Liu J. Word-level and sequential coding scheme of bit plane coding for EBCOT in JPEG2000. In: Proceeding of IEEE ISCE’05, 2005. 468–472.

  16. Xiong C, Hou J, Tian J, et al. Fast algorithm and architecture for embedded block coding. J Commun (in Chinese), 2006, 27(7): 53–60

    Google Scholar 

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Authors and Affiliations

  1. College of Electronic Information Engineering, South-Central University for Nationalities, Wuhan, 430074, China

    ChengYi Xiong

  2. Institute of Pattern Recognition & Artificial Intelligence, Key Laboratory of Education Ministry for Image Processing and Intelligent Control, Huazhong University of Science & Technology, Wuhan, 430074, China

    ChengYi Xiong, JinWen Tian & Jian Liu

Authors
  1. ChengYi Xiong
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  2. JinWen Tian
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  3. Jian Liu
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Corresponding author

Correspondence to ChengYi Xiong.

Additional information

Supported by the Natural Science Foundation of Hubei Province (Grant No. 2006ABA370), the Civil Research Project of State Defense (Grant No. C1120061304), the National Natural Science Foundation of China (Grant No. 60572048), the National High Technology Research and Development of China (863 Program) (Grant No. 2004AA119010-6)

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Xiong, C., Tian, J. & Liu, J. High performance word level sequential and parallel coding methods and architectures for bit plane coding. Sci. China Ser. F-Inf. Sci. 51, 337–351 (2008). https://doi.org/10.1007/s11432-008-0028-y

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  • DOI: https://doi.org/10.1007/s11432-008-0028-y

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