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Modular Verification of SPARCv8 Code

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Abstract

Inline assembly code is common in system software to interact with the underlying hardware platforms. The safety and correctness of the assembly code is crucial to guarantee the safety of the whole system. In this paper, we propose a practical Hoare-style program logic for verifying SPARC (Scalable Processor Architecture) assembly code. The logic supports modular reasoning about the main features of SPARCv8 ISA (instruction set architecture), including delayed control transfers, delayed writes to special registers, and register windows. It also supports relational reasoning for refinement verification. We have applied it to verify that there is a contextual refinement between a context switch routine in SPARCv8 and a switch primitive. The program logic and its soundness proof have been mechanized in Coq.

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Authors and Affiliations

  1. Department of Computer Science and Technology, Nanjing University, Nanjing, 210023, China

    Jun-Peng Zha & Xin-Yu Feng

  2. State Key Laboratory for Novel Software Technology, Nanjing University, Nanjing, 210023, China

    Jun-Peng Zha & Xin-Yu Feng

  3. Beijing Institute of Control Engineering, Beijing, 100080, China

    Lei Qiao

Authors
  1. Jun-Peng Zha
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  2. Xin-Yu Feng
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  3. Lei Qiao
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Correspondence to Xin-Yu Feng.

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Zha, JP., Feng, XY. & Qiao, L. Modular Verification of SPARCv8 Code. J. Comput. Sci. Technol. 35, 1382–1405 (2020). https://doi.org/10.1007/s11390-020-0536-9

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  • DOI: https://doi.org/10.1007/s11390-020-0536-9

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