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VLSI Architecture for Implementing OTFS

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Abstract

Orthogonal Time Frequency Space (OTFS) modulation is proposed to support high-speed and reliable vehicular communication scenarios, which is a novel two-dimensional (2D) delay-Doppler domain modulation technique. Compared with traditional modulation schemes such as orthogonal frequency division multiplexing (OFDM), OTFS has displayed better performance in very high-mobility wireless channels. In this work, we have proposed the novel VLSI architecture for OTFS in the Additive White Gaussian Noise (AWGN) channel condition and shown the resource utilization report of our proposed architecture to implement on Field Programmable Gate Array (FPGA) board, along with the relationship between inputs and outputs of the OTFS signal in the delay-Doppler domain.

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Funding

The authors declare that no funds, grants, or other support were received during the preparation of this manuscript.

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Author notes

  1. Suvra Sekhar Das and Indrajit Chakrabarti have contributed equally to this work.

Authors and Affiliations

  1. GSSST, IIT Kharagpur, Kharagpur, West Bengal, 721302, India

    Ashish Ranjan Shadangi & Suvra Sekhar Das

  2. E and ECE, IIT Kharagpur, Kharagpur, West Bengal, 721302, India

    Indrajit Chakrabarti

Authors
  1. Ashish Ranjan Shadangi
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  2. Suvra Sekhar Das
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  3. Indrajit Chakrabarti
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Contributions

All authors contributed to the study conception and design. The first draft of the manuscript was written by [Ashish Ranjan Shadangi] and all authors commented on the manuscript. All authors read and approved the final manuscript.

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Correspondence to Ashish Ranjan Shadangi.

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Shadangi, A.R., Das, S.S. & Chakrabarti, I. VLSI Architecture for Implementing OTFS. Wireless Pers Commun 137, 1931–1944 (2024). https://doi.org/10.1007/s11277-024-11488-3

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  • DOI: https://doi.org/10.1007/s11277-024-11488-3

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