Performance Modelling and Design Techniques for Efficiency Improvement in On-chip Switched-Capacitor DC-DC Converter

Fundamental charge vector method analysis is a single parameter optimization technique limited to conduction loss assuming all frequency-dependent switching (parasitic) loss negligible. This paper investigates a generalized structure to design DC-DC SC converters based on conduction and switching loss. A new technique is proposed to find the optimum value of switching frequency and switch size to calculate target load current and output voltage that maximize the efficiency. The analysis is done to identify switching frequency and switch size for two-phase 2:1 series–parallel SC converter for a target load current of 2.67 mA implemented on a 22 nm technology node. Results show that a minimum of 250 MHz switching frequency is required for target efficiency more than 90% and the output voltage greater than 0.85 V where the switch size of a unit cell corresponds to 10Ω on-resistance. MATLAB and PSpice simulation tools are used for results and validation.

V _out :

Target voltage (V)

I _load :

Load current (mA)

f _sw :

Switching frequency (MHz)

N _s :

Switch size (number of transistors connected in parallel for scaling transistor width)

R _SSL :

Slow switching limit impedance (Ω)

R _FSL :

Fast switching limit impedance (Ω)

R _out :

Output resistance (\(\sqrt {R_{SSL}^{2} + R_{FSL}^{2} }\), Ω)

C ₁ & C ₂ :

Flying/tank capacitors (pF)

C _bott :

Bottom plate capacitance of the flying capacitor (fF)

C _sw :

Switch parasitic gate capacitance (fF)

R _esr :

The equivalent series resistance of flying capacitor (Ω)

R _{on , i} :

On-resistance (drain to source) of an ith switch (Ω)

\(q_{c}^{j}\) :

Capacitor charge flow in the jth phase (C)

\(q_{r}^{j}\) :

Switch charge flow in jth phase (C)

\(q_{out}^{j}\) :

Output charge flow in the jth phase(C)

q _out :

Total output charge flow (C)

\(a_{c}^{j}\) :

Capacitor charge multiplier in the jth phase

a _out :

Charge multiplier for total output charge flow

a _in :

Charge multiplier for total input charge flow

C _i :

Capacitance for ith flying capacitor (pF)

\(a^{1}\) :

Capacitor charge multiplier vector in phase 1

\(a^{2}\) :

Capacitor charge multiplier vector in phase 2

\(a_{r}^{1}\) :

Switch charge multiplier vector in phase 1

\(a_{r}^{2}\) :

Switch charge multiplier vector in phase 2

a _{r , i} :

Charge multiplier of ith switch

a _r :

Total switch charge multiplier vector

D _i :

A duty cycle of the ith switch

n/m :

Converter transformation ratio

φ ₁ &φ ₂ :

Phase 1 and phase 2 (non-overlapping clock phase generation)

V _in :

Supply voltage (V)

P _{loss , ssl} :

Power loss due to SSL impedance (W)

P _{loss , fsl} :

Power loss due to FSL impedance (W)

P _RES :

Total conduction/resistive power loss (W)

V _{sw , cap} :

Switch blocking voltage (off state, V)

P _{loss , swcap} :

Power loss due to parasitic switch capacitor (W)

V _cap :

Bottom plate capacitor voltage (V)

P _{loss , bottcap} :

Power loss due to the bottom plate capacitor (W)

α :

The ratio of C_fly/C_bott

P _{loss , esr} :

Power loss due to ESR (W)

P _sw :

Total switching power loss (W)

V _{out , actual} :

Actual output voltage including R_load (V)

V _out :

Ideal output voltage (V)

V _{out , actual} /V _out :

Maximum power stage efficiency

P _out :

Total output power (W)

P _{total , loss} :

Total power loss (W)

η :

SC converter efficiency

k _R, k _C :

Process constant

W :

Width of the transistor (NMOS/PMOS)

Authors and Affiliations

1. Department of Electronics and Communication Engineering, Chandigarh College of Engineering and Technology, Chandigarh, India

   Sunita Saini & Davinder Singh Saini

Corresponding author

Correspondence to Davinder Singh Saini.

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