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Optimized Pipelined Fast Fourier Transform Using Split and Merge Parallel Processing Units for OFDM

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Abstract

This paper presents a new optimized design to implement Fast Fourier Transform in orthogonal frequency division multiplexing for real valued signals. The proposed method is a new pipelined design, it is the combination of serial as well as parallel split and merge processing butterfly units. The proposed design initially has a single processing unit, in second stage, processing unit splits into two parallel processing units, and thereafter from stage three onwards, merges into a single processing until the last stage. The proposed design is optimized to reduce the latency as well as the hardware complexity for real inputs and complex inputs, as real valued signals itself reduce half of the computations, redundant data paths are eliminated effectively by this design. The parallel processing unit speeds up the processing at the initial stage, whereas single processing units reduce the hardware complexity. This design is a solution for ambiguity between Latency and hardware. The proposed design is very effective for real valued signals. The proposed design is implemented in Radix-22 model, in which multipliers are required for every two stages. The proposed design reduces Latency parameter more than 50% with a small cost of adders and multipliers, also power consumption for higher order FFT’s is low.

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Authors and Affiliations

  1. Department of Electronics and Communication Engineering, JNTUK, Kakinada, India

    G. Prasanna Kumar & B. T. Krishna

  2. Department of Electronics and Communication Engineering, Shri Vishnu Engineering College, Bhimavaram, India

    K. Pushpa

Authors
  1. G. Prasanna Kumar
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  2. B. T. Krishna
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  3. K. Pushpa
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Correspondence to G. Prasanna Kumar.

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Appendix

Appendix

1.1 Latency Convergence Phenomenon

The latency convergence curve for 16-input pipelined FFT is with respect to parallel units is shown in Fig. 16, 1-parallel to 8-parallel units along x-axis and latency along y-axis. The curve clearly shows that 1-parallel designs has very high latency and 8-parallel design has no latency and as the number of parallel units increases Latency reduces.

Fig. 16
figure 16

Latency convergence curve

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The proposed design is in between 1 and 2 parallel designs, so that in the it is represented as 1.5. The proposed design with additional one BU unit placed based on the reduction of latency. The optimum reduction in latency is obtained by splitting the BU units in appropriate stage.

1.2 Optimum Reduction in Latency

Figure 17 shows the latency comparison of proposed split and merge designs, with different stages of splitting. The one parallel design has very high latency, split and merge in stage 2(sp2) has lower latency compared to third(sp3) and fourth stage(sp4) splitting.so that optimum reduction in latency is obtained with the splitting section in 1-parallel pipelined architecture is placed in stage-2.

Fig. 17
figure 17

Optimum reduction in latency using split and merge design

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1.3 Statistical Data Analysis of the Proposed Method

Figure 18 shows correlation analysis of the proposed design with some existing designs. in almost all designs throughput is highly correlated and utilization of hardware is moderately correlated. The statistical data analysis of the number of adders and latency is for N = 16 is measured in Rx643.5.3 with estimation package.

Fig. 18
figure 18

Correlation comparison Analysis of proposed design with existing designs

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The histogram of number adders and latency is shown in Fig. 19, it clearly shows that histogram is uniform, QQ plot is shown in Fig. 20. The correlation analysis shown in Fig. 21, it shows that the latency of proposed design is highly uncorrelated to existing designs, number of adders are weakly correlated to existing designs.

Fig. 19
figure 19

Histogram of adders and latency

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Fig. 20
figure 20

QQ plot of number of adders and latency

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Fig. 21
figure 21

Correlation analysis of number of adders and latency

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1.4 Butterfly Units (BU)

The internal operation of the Butterfly Unit is shown in Fig. 22, BU1, BU21 and BU22 are the butterfly units for processing real signals, Bu1 is the butterfly unit in stage -1, BU21 and BU22 are the two parallel butterfly units in stage-2, BU3 and BU4 are butterfly units in stage -3 and stage-4. The internal design of BU unit for real signal consists of two real adders, whereas for complex signals requires four real adders.

Fig. 22
figure 22

Butterfly unit. a Complex signals, b real signals

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Prasanna Kumar, G., Krishna, B.T. & Pushpa, K. Optimized Pipelined Fast Fourier Transform Using Split and Merge Parallel Processing Units for OFDM. Wireless Pers Commun 117, 3067–3089 (2021). https://doi.org/10.1007/s11277-020-07471-3

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