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Dual Antenna Receivers for High Data Rate Terminals

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Abstract

In this paper, dual antenna receiver architectures are studied including RAKE, chip-level linear equalizer, and their combination. The arithmetic complexity of single and dual antenna receiver methods is analyzed. Cost of such receivers when implemented with customized hardware or software on application-specific instruction set processors (ASIP) is estimated. The study shows that feasible dual antenna detection can be obtained with less than 70% additional costs. More flexible implementation supporting several standards can be obtained with software but it requires higher power consumption due to additional memory.

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Authors and Affiliations

  1. Nokia Corporation, P.O. Box 301, 00045, Nokia Group, Espoo, Finland

    Timo Viero

  2. Nokia Corporation, Oulu, Finland

    Kim Rounioja, Teemu Sipilä, Raimo Verkasalo & Jorma Lilleberg

  3. Tampere University of Technology, 33101, Tampere, Finland

    Jarmo Takala

Authors
  1. Timo Viero
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  2. Kim Rounioja
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  3. Teemu Sipilä
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  4. Raimo Verkasalo
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  5. Jarmo Takala
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  6. Jorma Lilleberg
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Corresponding author

Correspondence to Timo Viero.

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Viero, T., Rounioja, K., Sipilä, T. et al. Dual Antenna Receivers for High Data Rate Terminals. Wireless Pers Commun 43, 281–293 (2007). https://doi.org/10.1007/s11277-006-9221-8

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  • DOI: https://doi.org/10.1007/s11277-006-9221-8

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