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Low Complexity Reconfigurable DSP Circuit Implementations Based on Common Sub-expression Elimination

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Abstract

A design technique based on a combination of Common Sub-Expression Elimination and Bit-Slice (CSE-BitSlice) arithmetic for hardware and performance optimization of multiplier designs with variable operands is presented in this paper. The CSE-BitSlice technique can be extended to hardware optimization of multiplier circuits operating on vectors or matrices of variables. The CSE-BitSlice technique has been applied to the design and implementation of 12 × 12 and 42 × 42 bit real multipliers, a complex multiplier, a 6-tap FIR filter, and a 5-point DFT circuit. For comparison purposes, circuit implementations of the same arithmetic and DSP functions have been carried out using Radix-4 Booth and CSA algorithms. Simulation results based on implementations using the Xilinx FPGA 5VLX330FF1760-2 device shows that the circuits based on the CSE-BitSlice techniques require fewer logic resources and yield higher throughput as compared to the CSA and Radix-4 Booth based circuits.

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Authors and Affiliations

  1. Communications Research Centre, 3701 Carling Ave., Station H, Box 11490, Ottawa, Ontario, Canada, K2H 8S2

    H. Ho & V. Szwarc

  2. Department of Electronics, Carleton University, 1125 Colonel By Drive, Ottawa, Ontario, Canada, K1S 5B6

    T. Kwasniewski

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  1. H. Ho
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  2. V. Szwarc
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  3. T. Kwasniewski
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Correspondence to H. Ho.

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Ho, H., Szwarc, V. & Kwasniewski, T. Low Complexity Reconfigurable DSP Circuit Implementations Based on Common Sub-expression Elimination. J Sign Process Syst 61, 353–365 (2010). https://doi.org/10.1007/s11265-010-0458-9

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  • DOI: https://doi.org/10.1007/s11265-010-0458-9

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