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Transposed-Memory Free Implementation for Cost-Effective 2D-DCT Processor

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Abstract

This paper presents a cost-effective 2D-DCT processor based on a fast row/column decomposition approach. With a particular schedule, the processor does not require the transposed memory for 2D-DCT computing. We re-arrange the cosine coefficients of the first and second 1D-DCT transformations to keep DC-coefficient error free. The new architecture uses state-machines to generate cosine coefficients rather than ROM table, to save the memory cells and the address generator. For 8 × 8 DCT realization, the circuit only needs 36 adders without multipliers, and the whole chip uses about 19 k transistors. The chip area is about 4 mm 2 using TSMC 0.35 um CMOS process. The circuit complexity is only 1/3 ~ 1/5 of the conventional DCT chips.

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References

  1. Tayor, G. S., & Blair, G. M. (1998). Design for the discrete cosine transform in VLSI. IEE Proceedings on Computer Digital Technology, 145(2), 127–133. doi:10.1049/ip-cdt:19981911.

    Article  Google Scholar 

  2. Wallace, G. K. (1991). The JPEG still picture compression standard. Communications of the ACM, 34(4), 30–44. doi:10.1145/103085.103089.

    Article  Google Scholar 

  3. MPEG-2 video coder, ISO/IEC DIS 13818-2.

  4. Cote, G., Erol, B., & Kossentini, F. (1998). H.263+: video coding at low bit rate. IEEE Transactions on Circuits and Systems for Video Technology, 8(7), 849–866. doi:10.1109/76.735381.

    Article  Google Scholar 

  5. Feig, E., & Winograd, S. (1992). Fast algorithm for the discrete cosine transform. IEEE Transactions on Signal Processing, 40(Sept), 2174–2193. doi:10.1109/78.157218.

    Article  MATH  Google Scholar 

  6. Li, W. (1991). A new algorithm to compute the DCT and its inverse. IEEE Transactions on Signal Processing, 39(6), 1035–1313. doi:10.1109/78.136537.

    Article  Google Scholar 

  7. Cho, N. I., & Lee, S. U. (1991). Fast algorithm and implementation of 2-D discrete cosine transform. IEEE Transactions on Circuits and Systems, 38(3), 297–305. doi:10.1109/31.101322.

    Article  Google Scholar 

  8. Slawecki, D., & Li, W. (1992). DCT/IDCT processor design for high data rate coding. IEEE Transactions on Circuits and Systems for Video Technology, 2(2), 135–145. doi:10.1109/76.143413.

    Article  Google Scholar 

  9. Hsia, S. C., Liu, B. D., Yang, J. F., & Bai, B. L. (1992). VLSI implementation of parallel coefficient-by-coefficient two-dimensional IDCT processor. IEEE Transactions on Circuits and Systems for Video Technology, 5(5), 396–406 Oct. 1995.

    Article  Google Scholar 

  10. Chang, Y. T., & Wang, C. L. (1992). New systolic array implementation of the 2D discrete cosine transform and its inverse. IEEE Transactions on Circuits and Systems for Video Technology, 5(2), 150–157.

    Article  Google Scholar 

  11. Uramoto, S. I., Inoue, Y., Takabake, A., Yamashita, Y., Terane, H., & Yoshimoto, M. (1992). A 100 MHz 2-D discrete cosine transform core processor. IEEE Journal of Solid-State Circuits, 27(4), 492–498. doi:10.1109/4.126536.

    Article  Google Scholar 

  12. Madisetti, A., & Willson, N. (1995). A 100 MHz 2-D 8×8 DCT/IDCT processor for HDTV applications. IEEE Transactions on Circuits and Systems for Video Technology, 5(2), 158–164. doi:10.1109/76.388064.

    Article  Google Scholar 

  13. Aggoun, A., & Jalloh, I. (2003). Two-dimensional DCT/IDCT architecture. IEE Proceedings-Computers and Digital Techniques, 150(1), 2–10 20 Jan.

    Article  Google Scholar 

  14. Kyeounsoo, K. i. m., & Jong-Seog, K. o. h. (1999). An area efficient DCT architecture for MPEG-2 video encoder. IEEE Transactions on Consumer Electronics, 45(1), 62–67 Feb.

    Article  Google Scholar 

  15. Takala, J., Nikara, J., Akopian, D., Astola, J., & Saarinen, J. (2000). Pipeline architecture for 8*8 discrete cosine transform. IEEE International Conference on Acoustics, Speech, and Signal Processing, 2000. ICASSP ’00. Proc., 6, 3303–3306.

    Article  Google Scholar 

  16. Hsia S. C. (2003). An adaptive video coding control scheme for real-time MPEG applications. Journal on Applied Signal Processing, 245–251, Mar.

  17. Hsia, S.-C. (2003). Efficient memory IP design for HDTV coding applications. IEEE Transactions on Circuits and Systems for Video Technology, 13(6), 465–471. doi:10.1109/TCSVT.2003.813418.

    Article  Google Scholar 

  18. Samir, P. (1996). “ Verilog HDL,” Prentice Hall.

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Authors and Affiliations

  1. Department of Electronics Engineering and Department of Computer and Communication Engineering, National Kaohsiung First University of Science and Technology, Kaohsiung, 824, Taiwan, Republic of China

    Shih-Chang Hsia, Chin-Feng Tsai, Szu-Hong Wang & King-Chu Hung

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  1. Shih-Chang Hsia
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  2. Chin-Feng Tsai
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  3. Szu-Hong Wang
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  4. King-Chu Hung
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Corresponding author

Correspondence to Shih-Chang Hsia.

Additional information

This work was supported by National Science Council, Republic of China, under Grant NSC92-2213-E-327-010.

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Hsia, SC., Tsai, CF., Wang, SH. et al. Transposed-Memory Free Implementation for Cost-Effective 2D-DCT Processor. J Sign Process Syst Sign Image Video Technol 58, 161–172 (2010). https://doi.org/10.1007/s11265-009-0344-5

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  • DOI: https://doi.org/10.1007/s11265-009-0344-5

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