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Analysis and efficient implementation of IEEE-754 decimal floating point adders/subtractors in FPGAs for DPD and BID encoding

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Abstract

This paper proposes efficient implementations for addition/subtraction based on decimal floating point with Densely Packed Decimal (DPD) and Binary Integer Decimal (BID) encoding in FPGA devices. The designs use novel techniques based on the efficient utilization of dedicated resources in programmable devices. Implementations were made in Xilinx UltraScale+. For DPD adder/subtractor, they have computation times of 7.7 ns for Decimal32, 8.1 ns for Decimal64 and 8.5 ns for Decimal128. As for BID adder/subtractor, the computation time obtained is 13.5 ns for Decimal64. The proposed architecture achieves better computation times than related works. Compared to previous architectures, the proposed DPD implementation achieves 1.86\(\times\) speedup and 47% better LUT occupation. Also, the BID adder/subtractor achieves 3\(\times\) speedup and 5% less LUT occupation.

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Data availability

The data that support the findings of this study are openly available in GitHub at https://github.com/LabSET-UNICEN/, references [53, 59].

References

  1. Nannarelli A (2014) Decimal engine for energy-efficient multicore processors. In: 2014 22nd International Conference on Very Large Scale Integration (VLSI-SoC), pp. 1–6. https://doi.org/10.1109/VLSI-SoC.2014.7004176

  2. Dlodlo N, Mofolo M, Masoane L, Mncwabe S, Sibiya G, Mboweni L (2015) Research trends in existing technologies that are building blocks to the Internet of Things. In: Sobh T, Elleithy K (eds) Innovations and Advances in Computing, Informatics, Systems Sciences, Networking and Engineering. Springer, Cham, pp 539–548

    Chapter  Google Scholar 

  3. Cowlishaw MF (2003) Decimal floating-point: algorism for computers. In: Proceedings 2003 16th IEEE Symposium on Computer Arithmetic. IEEE, pp 104–111

  4. IEEE (2008) IEEE Standard for floating-point arithmetic. IEEE Std 754-2008. https://doi.org/10.1109/IEEESTD.2008.4610935

  5. Duale AY, Decker MH, Zipperer H-G, Aharoni M, Bohizic TJ (2007) Decimal floating-point in z9: an implementation and testing perspective. IBM J Res Dev 51(1.2):217–227. https://doi.org/10.1147/rd.511.0217

    Article  Google Scholar 

  6. Eisen L, Ward JW, Tast H-W, Mading N, Leenstra J, Mueller SM, Jacobi C, Preiss J, Schwarz EM, Carlough SR (2007) IBM POWER6 accelerators: VMX and DFU. IBM J Res Dev 51(6):1–21. https://doi.org/10.1147/rd.516.0663

    Article  Google Scholar 

  7. Schwarz EM, Kapernick JS, Cowlishaw MF (2009) Decimal floating-point support on the IBM system z10 processor. IBM J Res Dev 53(1):4–1410. https://doi.org/10.1147/JRD.2009.5388585

    Article  Google Scholar 

  8. IBM (2021) IBM z15 Technical Introduction. https://www.redbooks.ibm.com/redbooks/pdfs/sg248850.pdf

  9. IBM (2021) IBM Power E1080: Technical Overview and Introduction. https://www.redbooks.ibm.com/redpapers/pdfs/redp5649.pdf

  10. Batista F (2020) Decimal data type, version 2003. http://www.python.org/dev/peps/pep-0327

  11. Cowlishaw MF (2010) The decnumber library, v3.68. http://speleotrove.com/decimal/ decnumber.pdf

  12. Crismer P (2019) Eiffel decimal arithmetic library. http://www.gobosoft.com/eiffel/gobo/ math/decimal/index.html

  13. Currie D (2007) Lua decnumber library. http://files.luaforge.net/releases/ldecnumber/ldecnumber/ldecNumber-21

  14. Dorrigiv M, Jaberipur G (2014) Low area/power decimal addition with carry-select correction and carry-select sum-digits. Integration 47(4):443–451. https://doi.org/10.1016/j.vlsi.2014.01.004

    Article  Google Scholar 

  15. Cornea M, Harrison J, Anderson C, Tang P, Ping T, Schneider E, Gvozdev E (2009) A software implementation of the IEEE 754R decimal floating-point arithmetic using the binary encoding format. IEEE Trans Comput 58(2):148–162. https://doi.org/10.1109/TC.2008.209

    Article  MathSciNet  Google Scholar 

  16. Anderson MJ, Tsen C, Wang L, Compton K, Schulte MJ (2009) Performance analysis of decimal floating-point libraries and its impact on decimal hardware and software solutions, pp 465–471

  17. Schulte MJ, Lindberg N, Laxminarain A (2005) Performance evaluation of decimal floating-point arithmetic. In: Proceedings of the 6th IBM Austin Center for Advanced Studies Conference, vol 14. CiteSeer

  18. Cowlishaw MF (2002) Densely packed decimal encoding. In: IEEE Proceedings of the Computers and Digital Techniques, vol 149. IEEE, pp 102–104

  19. Bhat M, Crawford J, Morin R, Shiv K (2007) Performance characterization of decimal arithmetic in commercial java workloads. In: 2007 IEEE International Symposium on Performance Analysis of Systems & Software. IEEE, pp 54–61

  20. Vazquez A, Antelo E (2009) A high-performance significand BCD adder with IEEE 754-2008 decimal rounding. In: 19th IEEE Symposium on Computer Arithmetic, ARITH 2009. IEEE, pp 1335–144

  21. Vázquez M, Todorovich E (2016) FPGA-specific decimal sign-magnitude addition and subtraction. Int J Electron 103(7):1166–1185. https://doi.org/10.1080/00207217.2015.1089945

    Article  Google Scholar 

  22. Vázquez M, Leiva L, Sutter G (2019) Radix-10 decimal logarithm by direct selection for 6-input LUTs programmable devices. Microprocess Microsyst 64:143–158. https://doi.org/10.1016/j.micpro.2018.11.001

    Article  Google Scholar 

  23. Vázquez M, Tosini M, Leiva L (2021) Radix-10 restoring square root for 6-input LUTs programmable devices. Circuits Syst Signal Process. https://doi.org/10.1007/s00034-020-01571-y

    Article  Google Scholar 

  24. Xilinx (2016) 7 Series FPGAs configuration-user guides. www.xilinx.com

  25. Xilinx (2018) Ultrascale architecture and product Data sheet: Overview. www.xilinx.com

  26. Tsen C, Gonzalez-Navarro S, Schulte M (2007) Hardware design of a binary integer decimal-based floating-point adder. In: 2007 25th International Conference on Computer Design, pp 288–295. https://doi.org/10.1109/ICCD.2007.4601915

  27. Farmahini-Farahani A, Tsen C, Compton K (2009) FPGA implementation of a 64-bit bid-based decimal floating-point adder/subtractor. In: 2009 International Conference on Field-Programmable Technology, pp 518–521. https://doi.org/10.1109/FPT.2009.5377636

  28. Erle MA (2009) Algorithms and Hardware Designs for Decimal Multiplication. Lehigh University, Bethlehem

    Google Scholar 

  29. Schmookler MS, Weinberger A (1971) High speed decimal addition. IEEE Trans Comput C 20(8):862–866. https://doi.org/10.1109/T-C.1971.223362

    Article  Google Scholar 

  30. Veeramachaneni S, Krishna MK, Avinash L, Reddy PS, Srinivas MB (2007) Novel, high-speed 16-digit BCD adders conforming to IEEE 754R format. In: IEEE Computer Society Annual Symposium on VLSI (ISVLSI’07), pp 343–350. https://doi.org/10.1109/ISVLSI.2007.71

  31. Bayrakci A, Akass A (2007) Reduced delay BCD adder. In: IEEE International Conference on Application-Specific Systems, Architectures and Processors. IEEE, pp 266–271 (2007)

  32. Juang T-B, Peng H-H, Kuo H-L (2012) Parallel and digit-serial implementations of area-efficient 3-operand decimal adders. In: 2012 International SoC Design Conference (ISOCC), pp 239–242. https://doi.org/10.1109/ISOCC.2012.6407084

  33. Svoboda A (1969) Decimal adder with signed digit arithmetic. IEEE Trans Comput C 18(3):212–215. https://doi.org/10.1109/T-C.1969.222633

    Article  Google Scholar 

  34. Shirazi B, Yun DYY, Zhang CN (1989) RBCD: redundant binary coded decimal adder. IEEE Proc E (Comput Digit Tech) 136:156–1604

    Article  Google Scholar 

  35. Han L, Chen D, Wahid KA, Ko S-B (2011) Nonspeculative decimal signed digit adder. In: 2011 IEEE International Symposium of Circuits and Systems (ISCAS), pp 1053–1056. https://doi.org/10.1109/ISCAS.2011.5937750

  36. Han L, Ko S-B (2013) High-speed parallel decimal multiplication with redundant internal encodings. IEEE Trans Comput 62(5):956–968. https://doi.org/10.1109/TC.2012.35

    Article  MathSciNet  Google Scholar 

  37. Yehia K, Fahmy HAH, Hassan M (2010) A redundant decimal floating-point adder. In: 2010 Conference Record of the Forty Fourth Asilomar Conference on Signals, Systems and Computers, pp 1144–1147. https://doi.org/10.1109/ACSSC.2010.5757583

  38. Bioul G, Vazquez M, Deschamps J, Sutter G (2010) High-speed FPGA 10’s complement adders–subtractors. Int J Reconfig Comput 2010:219764–121976414

    Article  Google Scholar 

  39. Vázquez A (2009) High-performance decimal floating-point units. PhD Thesis, Universidade de Santiago de Compostela

  40. Wang L-K, Schulte MJ (2007) Decimal floating-point adder and multifunction unit with injection-based rounding. In: 18th IEEE Symposium on Computer Arithmetic (ARITH ’07), pp. 56–68. https://doi.org/10.1109/ARITH.2007.13

  41. Kenney RD, Schulte MJ (2005) High-speed multioperand decimal adders. IEEE Trans Comput 54(8):953–963. https://doi.org/10.1109/TC.2005.129

    Article  Google Scholar 

  42. Gorgin S, Jaberipur G (2009) A fully redundant decimal adder and its application in parallel decimal multipliers. Microelectron J 40(10):1471–1481. https://doi.org/10.1016/j.mejo.2009.07.002

    Article  Google Scholar 

  43. Vazquez A, de Dinechin F (2010) Multi-operand decimal tree adders for FPGAs. Research Report

  44. Neto H, Véstias M (2017) Decimal addition on FPGA based on a mixed BCD/excess-6 representation. Microprocess Microsyst 55:91–99. https://doi.org/10.1016/j.micpro.2017.10.004

    Article  Google Scholar 

  45. Véstias M, Neto H (2021) Decimal multiplication in FPGA with a novel decimal adder/subtractor. Algorithms 14:198. https://doi.org/10.3390/a14070198

    Article  Google Scholar 

  46. Bennedek M (1977) Developing large binary to BCD conversion structures. IEEE Trans Comput C 26(7):688–700

    Article  Google Scholar 

  47. Iguchi Y, Sasao T, Matsuura M (2007) On designs of radix converters using arithmetic decompositions—binary to decimal converters. In: 37th International Symposium on Multiple-Valued Logic (ISMVL07). IEEE Computer Society, Los Alamitos, p 32. https://doi.org/10.1109/ISMVL.2007.39

  48. Nicoud J-D (1971) Iterative arrays for radix conversion. IEEE Trans Comput C 20(12):1479–1489. https://doi.org/10.1109/T-C.1971.223160

    Article  Google Scholar 

  49. Thompson J, Karra N, Schulte MJ (2004) A 64-bit decimal floating-point adder. In: IEEE Computer Society Annual Symposium on VLSI, pp 297–298. https://doi.org/10.1109/ISVLSI.2004.1339563

  50. Wang L-K, Schulte MJ, Thompson JD, Jairam N (2009) Hardware designs for decimal floating-point addition and related operations. IEEE Trans Comput 58(3):322–335. https://doi.org/10.1109/TC.2008.147

    Article  MathSciNet  Google Scholar 

  51. Minchola C, Vazquez M, Sutter G (2011) A FPGA IEEE-754-2008 decimal64 floating-point adder/subtractor. In: 2011 VII Southern Conference on Programmable Logic (SPL), pp 251–256. https://doi.org/10.1109/SPL.2011.5782657

  52. Tsen C, Schulte M, Gonzalez-Navarro S (2007) Hardware design of a binary integer decimal-based ieee p754 rounding unit. In: 2007 IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), pp 115–121. https://doi.org/10.1109/ASAP.2007.4429967

  53. LabSET (2022) VHDL implementation of DPD encoded adder/subtractor. https://github.com/LabSET-UNICEN/DPD-Adder-Subtractor

  54. Xilinx (2018) Vivado design suite user guide-design flows overview. www.xilinx.com

  55. Xilinx (2018) Vivado design suite user guide-synthesis. www.xilinx.com

  56. Xilinx (2013) ISE design suite 14: Release notes, installation and licensing. www.xilinx.com

  57. Xilinx (2013) XST user guide for virtex-6, spartan-6 and 7 series devices. www.xilinx.com

  58. Milenković N, Stankovic V, Milić M (2015) Modular design of fast leading zeros counting circuit. J Electr Eng 66:329–333. https://doi.org/10.2478/jee-2015-0054

    Article  Google Scholar 

  59. LabSET (2022) VHDL implementation of BID encoded adder/subtractor. https://github.com/LabSET-UNICEN/BID-Adder-Subtractor

  60. Cornea M, Anderson C, Harrison J, Tak P, Tang P, Schneider E, Tsen C (2007) An implementation of the IEEE 754R decimal floating-point arithmetic using the binary encoding format. In: Proceedings of the 18th IEEE Symposium on Computer Arithmetic. IEEE Computer Society, Montpellier, France, pp 29–37

  61. Xilinx (2017) ADM-PCIE-7V Data sheet. www.xilinx.com

  62. Amazon (2017) Amazon EC2 F1 Instance. https://aws.amazon.com/ec2/instance-types/f1/

  63. Choi Y-K, Cong J, Fang Z, Hao Y, Reinman G, Wei P (2019) In-depth analysis on microarchitectures of modern heterogeneous CPU-FPGA platforms. ACM Trans Reconfig Technol Syst. https://doi.org/10.1145/3294054

    Article  Google Scholar 

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Funding

Partial financial support was received from the Research Secretary of the Faculty of Engineering of FASTA University and SeCAT of UNICEN University.

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Author notes

  1. Marcelo Tosini, Martín Vázquez and Lucas Leiva have contributed equally to this work.

Authors and Affiliations

  1. Computer and Systems Department, UNICEN, Pinto 399, 7000, Tandil, Buenos Aires, Argentina

    Marcelo Tosini, Martín Vázquez & Lucas Leiva

  2. Engineering Faculty, FASTA University, Gascón 3145, 7600, Mar del Plata, Buenos Aires, Argentina

    Marcelo Tosini, Martín Vázquez & Lucas Leiva

Authors
  1. Marcelo Tosini
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  2. Martín Vázquez
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MT and MV helped in conceptualization, methodology, and experimentation. MT, MV, and LL were involved in writing, review, and editing .

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Correspondence to Marcelo Tosini, Martín Vázquez or Lucas Leiva.

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Tosini, M., Vázquez, M. & Leiva, L. Analysis and efficient implementation of IEEE-754 decimal floating point adders/subtractors in FPGAs for DPD and BID encoding. J Supercomput 80, 9298–9326 (2024). https://doi.org/10.1007/s11227-023-05808-w

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