Abstract
Graph embedding maps a guest graph into a host graph, thus enabling structural simulation, processor allocation, and algorithm porting. It is used to design the physical layout of Network-on-Chip (NoC) and to study the simulation capabilities of a parallel architecture. Wirelength is one of the indicators to measure the quality of graph embedding. Minimum wirelength in NoC design means a smaller wiring area and less wiring cost. In parallel computing, it means shorter communication time and delay. In this paper, the guest graph is the hierarchical folded cube with good communication and fault tolerance capabilities. The host graphs are the linear array and the complete binary tree, both of which are widely used in graph embeddings. We solve the embedding problems in linear time for hierarchical folded cubes into linear arrays and complete binary trees with minimum wirelength, respectively.
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Acknowledgements
This work is supported by the National Natural Science Foundation of China (No. U1905211), A Project Funded by the Priority Academic Program Development of Jiangsu Higher Education Institutions (PAPD), Natural Science Foundation of China under grant (No. 62102196), Natural Science Foundation of Jiangsu Province (No. BK20200753), Jiangsu Postdoctoral Science Foundation Funded Project (No. 2021K096A), the Future Network Scientific Research Fund Project (No. FNSRFP-2021-YB-60), the Natural Science Fund for Colleges and Universities in Jiangsu Province(No. 21KJB520026), and the Fundamental Research Funds for the Central Universities of Jilin University (No. 93K172020K25).
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Guo, R., Wang, Y., Fan, J. et al. Embedding hierarchical folded cubes into linear arrays and complete binary trees with minimum wirelength. J Supercomput 79, 11300–11327 (2023). https://doi.org/10.1007/s11227-023-05095-5
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DOI: https://doi.org/10.1007/s11227-023-05095-5