Abstract
With the development of Internet of Things (IoT), real-time decision making has gradually become one of the important characteristics in mobile edge computing (MEC) environment of IoT. Therefore, in the Integrated Circuit (IC) design of MEC environment for IoT, low delay is one of the important optimization objectives. In the many routing competitions, wirelength, overflow, and runtime are the main evaluation standards, so how to reduce wirelength, overflow, and runtime has become a major challenge. However, the existing work lacks the excellent optimization ability in wirelength, overflow, and runtime, or only considers some of the optimization objectives. Therefore, we consider the wirelength, overflow, and runtime as the optimization objectives and propose a high-quality global routing algorithm of IC design in MEC environment, including the following effective strategies: (1) A hybrid topology optimization strategy combining Prim algorithm and divide-and-conquer method, (2) a heuristic search algorithm considering the congestion and the wirelength of nets. Due to the use of the Fast Lookup Table (FLUTE) algorithm to construct the topology of each net, there are too many Steiner points. For this reason, we used Prim algorithm and divide-and-conquer method to construct the topology, and thus it can avoid the problem of redundant Steiner points. In addition, we propose a congestion area identification method based on interval division to determine the area and order of nets to rip-up and reroute (R&R). Furthermore, a heuristic search algorithm that considers both the congestion and the wirelength of nets is used to optimize the total wirelength in the R&R stage. In terms of the total overflow, the total wirelength and the runtime, the experimental results show that the proposed strategies have achieved effective optimization, which can better satisfy the demand of low delay of IC design for data processing in MEC environments of IoT.
Similar content being viewed by others
References
Habib ur Rehman M, Jayaraman P, Malik SUR, et al (2017) Rededge: a novel architecture for big data processing in mobile edge computing environments. J Sens Actuator Netw 6(3):17
Kaur MJ (2019) A comprehensive survey on architecture for big data processing in mobile edge computing environments. Edge Computing 33–49
Jha DN, Alwasel K, Alshoshan A et al (2020) IoTSim-edge: a simulation framework for modeling the behavior of Internet of Things and edge computing environments software. Pract Exp 50(6):844–867
Mahmud R, Buyya R (2019) Modelling and simulation of fog and edge computing environments using iFogSim toolkit. Fog and edge computing: Principles and paradigms 1–35
Xu N, Hong X (2009) Very large scale integration physical design theory and method. Tsinghua University Press, Beijing
Lu L (2017) Physical design challenges and innovations to meet power, speed, and area scaling trend. In: Proceedings of International Symposium on Physical Design. New York: ACM Press, pp 63
Zhu Z, Chen J, Zhu W (2016) A global routing algorithm based on multistage rip-up and reroute. J Comput Aided Des Comput Graph 28(11):2000–2008
Tang H, Liu G, Chen X et al (2020) A survey on steiner tree construction and global routing for VLSI design. IEEE Access 68593–68622
Chen X, Liu G, Xiong N et al (2020) A survey of swarm intelligence techniques in VLSI routing problems. IEEE Access 26266–26292
Liu G, Zhuang Z, Guo W et al (2019) RDTA: An efficient routability-driven track assignment algorithm. In: Proceedings of ACM Great Lakes Symposium on VLSI. New York: ACM Press, pp 315–318
Guibas LJ, Stolfi J (1983) On computing all north-east nearest neighbors in the L1 metric. Inf Process Lett 11(17):219–223
Chen C, Guo R, Zhang W et al (2021) Optimal sequential relay-remote selection and computation offloading in mobile edge computing. J Supercomput 1–24
Li C, Cai Q, Zhang C et al (2021) Computation offloading and service allocation in mobile edge computing. J Supercomput 1–30
Chen X, Li A, Zeng X et al (2015) Runtime model based approach to IoT application development. Front Comp Sci 9(4):540–553
Xue X, Wu X, Jiang C et al (2021) Integrating sensor ontologies with global and local alignment extractions. Wirel Commun Mob Comput 6625184:1–10
Xue X, Yang C, Jiang C et al (2021) Optimizing ontology alignment through linkage learning on entity correspondences. Complexity 5574732:1–12
Lin B, Huang Y, Zhang J et al (2020) Cost-driven offloading for dnn-based applications over cloud, edge and end devices. IEEE Trans Ind Inf 16(8):5456–5466
Chen X, Lin J, Ma Y, Lin J, Wang H, Huang G (2019) Self-adaptive resource allocation for cloud-based software services based on progressive QoS prediction model. Sci China Inf Sci 62(11):1–3
Chen X, Wang H, Ma Y et al (2020) Self-adaptive resource allocation for cloud-based software services based on iterative QoS prediction model. Future Gen Comput Syst 105:287–296
Huang G, Ma Y, Liu X et al (2015) Model-based automated navigation and composition of complex service mashups. IEEE Trans Serv Comput 8(3):494–506
Huang G, Liu X, Ma Y et al (2019) Programming situational mobile web applications with cloud-mobile convergence: an internetware-oriented approach. IEEE Trans Serv Comput 12(1):6–19
Liu X, Huang G, Zhao Q et al (2014) iMashup: a mashup-based framework for service composition. Sci China Inf Sci 54(1):1–20
Li W, Jin S (2021) Performance evaluation and optimization of a task offloading strategy on the mobile edge computing with edge heterogeneity. J Supercomput 1–22
Huang G, Xu M, Lin X et al (2017) ShuffleDog: characterizing and adapting user-perceived latency of android apps. IEEE Trans Mob Comput 16(10):2913–2926
Liu J, Pui CW, Wang F et al (2020) CUGR:detailed-routability-driven 3D global routing with probabilistic resource model. In: 2020 57th ACM/IEEE Design Automation Conference (DAC) 1–6
Tang H, Liu G, Chen X et al (2020) A survey on steiner tree construction and global routing for VLSI design. IEEE Access 8:68593–68622
Liu G, Yang L, Xu S et al (2021) X-architecture Steiner minimal tree algorithm based on multi-strategy optimization discrete differential evolution. PeerJ Comput Sci 7:e473
Liu G, Chen X, Zhou R et al (2021) Social learning discrete Particle Swarm Optimization based two-stage X-routing for IC design under Intelligent Edge Computing architecture. Appl Soft Comput 104(6):107215
Liu G, Zhang X, Guo W et al (2021) Timing-aware layer assignment for advanced process technologies considering via pillars. IEEE Trans Comput Aided Des Integr Circuits Syst
Liu G, Zhu W, Xu S et al (2020) Efficient VLSI routing algorithm employing novel discrete PSO and multi-stage transformation. J Ambient Intell Hum Comput 1–16
Xue X, Zhang J (2021) Matching large-scale biomedical ontologies with central concept based partitioning algorithm and adaptive compact evolutionary algorithm. Appl Soft Comput 106:1–11
Liu G, Chen Z, Zhuang Z et al (2020) A unified algorithm based on HTS and self-adapting PSO for the construction of octagonal and rectilinear SMT. Soft Comput 24(6):3943–3961
Liu G, Guo W, Li R et al (2015) XGRouter: high-quality global router in X-architecture with particle swarm optimization. Front Comp Sci 9(4):576–594
Liu G, Guo W, Niu Y et al (2015) A PSO-based timing-driven octilinear steiner tree algorithm for VLSI routing considering bend reduction. Soft Comput 19(5):1153–1169
Liu G, Huang X, Guo W et al (2015) Multilayer obstacle-avoiding X-architecture steiner minimal tree construction based on particle swarm optimization. IEEE Trans Cybern 45(5):989–1002
Carden R, Li J, Cheng C (1996) A global router with a theoretical bound on the optimal solution. IEEE Trans Comput Aided Des Integr Cicuits Syst 15(2):208–216
Albrecht C (2021) Global routing by new approximation algorithms for multicommodiy flow. IEEE Trans Comput Aided Des Integr Cicuits Syst 20(50):622–632
Cho M, Lu K, Yuan K et al (2007) BoxRouter 2.0: Architecture and implementation of a hybrid and robust global router. Proceedings of International Conference on Computer-Aided Design. Los Alamitos: IEEE Computer Society Press, pp 503–508
Liu G, Zhuang Z, Guo W et al (2020) A high performance X-architecture multilayer global router for VLSI. Acta Autom Sin 46(1):79–93
Hadsell RT, Madden PH (2003) Improved global routing through congestion estimation Proceedings of Design Automation Conference. ACM Press, New York, pp 28–31
Kastner R, Bozorgzadeh E, Sarrafzadeh M (2002) Pattern routing: Use and theory for increasing predictability and avoiding coupling. IEEE Trans Comput Aided Des Integr Cicuits Syst 21(7):777–790
Cao Z, Jing T, Xiong J et al (2007) DpRouter: a fast and accurate dynamic-pattern-based global routing algorithm. In: Proceedings of Asia and South Pacific Design Automation Conference. Los Alamitos: IEEE Computer Society Press, pp 256–261
Pan M, Chu C (2007) FastRoute 2.0: A high-quality and efficient global router. In: Proceedings of Asia and South Pacific Design Automation Conference. Los Alamitos: IEEE Computer Society Press, pp 250–255
Chang Y, Lee Y, Gao JR et al (2010) NTHU-Route 2.0: a robust global router for modern designs. IEEE Tran Comput Aided Des Integr Cicuits Syst 29(12):1931–1944
Chu C, Wong YC (2008) FLUTE: fast lookup table based rectilinear Steiner minimal tree algorithm for VLSI design. IEEE Tran Comput Aided Des Integr Cicuits Syst 27(1):70–83
Pan M, Chu C (2006) FastRoute: a step to integrate global routing into placement. In; Proceedings of International Conference on Computer Aided Design. Los Alamitos: IEEE Computer Society Press, pp 464–471
Lee T, Wang T (2008) Congestion-constrained layer assignment for via minimization in global routing. IEEE Tran Comput Aided Des Integr Cicuits Syst 27(8):1643–1656
Prim R (1957) Shortest connection networks and some generalizations. Bell Syst Tech J 36(6):1389–1401
ISPD 2008 Global Routing Contest [Online]. Available: http://www.sigda.org/ispd2008/contests/ispd08rc.html
Liao P, Wang T (2018) A Bus-Aware Global Router. In: Proceedings of Synthesis and System Integration of Mixed Information Technologies. Kyoto: IEICE ESS Fundamentals Review, pp 20–25
Zhu W, Zhang X, Liu G et al (2020) MiniDeviation: an efficient multi-stage bus-aware global router. In: 2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), pp 1–4
Acknowledgements
This work was partially supported by the National Natural Science Foundation of China under Grants No. 61877010 and No. 11501114, National Basic Research Program of China under Grant No. 2011CB808000, State Key Laboratory of Computer Architecture (ICT,CAS) under Grant No. CARCHB202014, Fujian Natural Science Funds under Grants No. 2019J01243 and No. 2018J07005, and Fuzhou University under Grants No. GXRC-20060 and No. XRC-1544.
Author information
Authors and Affiliations
Corresponding author
Additional information
Publisher's Note
Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.
Rights and permissions
About this article
Cite this article
Xu, S., Wei, L., Liu, G. et al. A high-quality global routing algorithm based on hybrid topology optimization and heuristic search for data processing in MEC. J Supercomput 78, 7133–7157 (2022). https://doi.org/10.1007/s11227-021-04147-y
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s11227-021-04147-y