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Design of reconfigurable array processor for multimedia application

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Abstract

With the rapid growth of the amount of computations and power consumption, there is a pressing need for a high power-efficiency architecture, which takes account of computational efficiency and flexibility of application. This paper proposes a type of array-processor architecture for multimedia application which is programmable and self-reconfigurable and consists of 1024 thin-core processing elements (PE). The performance and power dissipation are demonstrated with different multimedia application algorithms such as hash, and fractional motion estimation (FME). The results show that the proposed architecture can provide high performance with less energy consumption using parallel computation.

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Acknowledgments

This work was supported by the National Natural Science Foundation of China (61272120, 61602377, and 61634004), the Natural Science Foundation of Shaanxi Province of China (2015JM6326), Shaanxi Provincial Co-ordination Innovation Project of Science and Technology (2016KTZDGY02-04-02), and the Project of Education Department of Shaanxi Provincial Government (15JK1683).

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Correspondence to Lin Jiang.

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Yun, Z., Jiang, L., Wang, S. et al. Design of reconfigurable array processor for multimedia application. Multimed Tools Appl 77, 3639–3657 (2018). https://doi.org/10.1007/s11042-017-5284-7

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  • DOI: https://doi.org/10.1007/s11042-017-5284-7

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