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Enhanced Authentication Using Hybrid PUF with FSM for Protecting IPs of SoC FPGAs

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Abstract

A new generation of technology is harder and costlier to deliver because of the physical design limitations of the silicon chip. The minute chip alone is not only compromising the requirements of the user but also creates challenges with respect to security. Architecture for two-factor authentication is designed with low-power, area and with less- human intervention. The proposed model consists of hybrid physical unclonable functions (PUFs) and finite state machine (FSM), which is used to secure the chip and intellectual property (IP) respectively. The PUFs are most often used in recent security applications such as IP protection, IC metering, hardware signature, and obfuscation. This application needs a complex algorithm with a database which consumes more cost and time. In this paper, we have proposed an authentication model consisting of strong and weak PUF with an FSM which can be used for IoT applications. The main focus of this proposal is to authenticate hardware and software IP in circuits. The Experimental evaluation illustrates that the area and power consumed are 5% and 9%, respectively, for authenticating 26 IPs with no false acceptance ratio (FAR) and 1% false rejection ratio (FRR).

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Authors and Affiliations

  1. Department of Computer Science and Engineering, National Institute of Technology, Tiruchirappalli, India

    J. Kokila &  N. Ramasubramanian

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  1. J. Kokila
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  2. N. Ramasubramanian
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Correspondence to J. Kokila.

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J. Kokila, N. Ramasubramanian Enhanced Authentication Using Hybrid PUF with FSM for Protecting IPs of SoC FPGAs. J Electron Test 35, 543–558 (2019). https://doi.org/10.1007/s10836-019-05808-w

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  • DOI: https://doi.org/10.1007/s10836-019-05808-w

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