Abstract
This paper addresses the modeling and simulation of power supply voltage transients (Δ V DD ) in digital SoC (Systems on a Chip), namely their impact on SoC core’s performance. The goal is to verify, in a cost-effective way, core’s fault tolerance to this disturbance, aiming at EMI/EMC standard compliance. The two key parameters are the time slack and the defect size. A top-down approach is used to introduce an innovative fault injection and simulation technique. In fact, fault simulation is carried out either by using faulty delays (defect size as a function of Δ V DD magnitude) in the CUT (Core Under Test) and nominal time excitation rate, or by using a fault-free CUT description and faster test application times (speed-up proportional to Δ V DD magnitude). A bottom-up approach, using electrical simulation, is extensively used to demonstrate the adequacy of exploiting this duality between time excitation and delay response, for combinational CUT. We refer this duality as the “accordion” effect. For sequential circuits, and for pipeline circuits, it is shown that the tolerance to Δ V DD disturbances is significantly lower than the one observed in combinational CUT, due to de-synchronization effects in storage elements. This effect depends on the clock distribution network and is a consequence of differently delayed responses of the CUT and of the clock network. Results are demonstrated using basic infrastructures and ISCAS benchmark circuits.
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Daniel Barros Jr. received the B.S. and the M.Sc. degrees in Electrical Engineering from the Catholic University (PUCRS), Brazil in 1999 and 2002, respectively. Since 2002 he is Associate Professor at the same university. His research interests are Pattern Recognition, Design for Testability, BIST, and FPGA-Based Fast Prototyping.
Marcial Jesús Rodríguez Irago received his M.Sc. degree in Electrical and Computer Engineering (Telecommunications and Microelectronics) in 2002 from University of Vigo (Spain). He is finishing his Ph.D. work in the area of dynamic faults and delay testing. He is a researcher at INESC-ID, in the Quality, Test and Hardware/Software Co-design (QTHS) Group, and University of Vigo, in the Department of Electronics Technology. His research interests include delay testing, dynamic faults and full-custom design (including microwave IC design).
Marcelino Bicho dos Santos} has got his degree on Electrical and Computer Engineering, in 1990, and his M.Sc. degree in 1994, at IST (Instituto Superior Técnico) from the Technical University of Lisbon. He is finishing his Ph.D. work at IST in the area of defect-oriented HDL test preparation. He is a researcher at INESC-ID (Instituto de Engenharia de Sistemas e Computadores), in the Quality, Test and Hardware/Software Co-design (QTHS) Group. His scientific and technical interests include defect-oriented test, DFT, BIST, IDDX testing, low-power testing, and system-level fault modeling and simulation.
Isabel Maria Cacho Teixeira} has got her degree in Electrical Engineering (Telecommunications and Electronics) and her Ph.D. in Applied Electronics, in 1984, by IST from the Technical University of Lisbon. She is currently an Associate Professor at IST. She holds a Senior researcher position at INESC-ID, where she is co-chairing the Quality, Test and Hardware/Software Co-design (QTHS) Group. Her scientific and technical interests include the analysis, specification, co-design and test of hardware/software systems, Object-Oriented Modeling techniques, CAD and information systems design.
Fabian Vargas received his B.S. degree in EE from the Catholic University (PUCRS), Brazil, in 1988, the M.Sc. degree in CS from the Federal University of Rio Grande do Sul (UFRGS), also in Brazil, in 1991, and the Ph.D. degree from the Institut National Polytechnique de Grenoble (INPG), France, in 1995. Since 1996 he is Associate Professor at the Catholic University (PUCRS). In 1997 he founded and chaired since then the Latin American Group of the IEEE Computer Society—Test Technology Technical Council (TTTC). Prof. Vargas is an IEEE Computer Society Golden Core Member. His research interests include Fault-Tolerant Systems Design, On-Line Testing, and Reliability-Driven Hardware-Software Partitioning.
João Paulo Teixeira has got his degree in Electrical Engineering (Telecommunications and Electronics) and his Ph.D. in Applied Electronics in 1982, at IST from the Technical University of Lisbon. He is currently an Associate Professor at IST. He is a Senior researcher at INESC-ID, where he is co-chairing the QTHS Group. His R&D interests include the analysis, specification, design, production and test of hardware/software systems, which use microelectronics as supporting technologies. Emphasis is given to the design and test of digital, analog and mixed-signal circuits and systems, implemented in CMOS or CMOS-compatible semiconductor technologies, and to the development of EDA (Electronic Design Automation) tools, especially CAT (Computer-Aided Testing) tools.
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Júnior, D.B., Rodriguez-Irago, M., Santos, M.B. et al. Fault Modeling and Simulation of Power Supply Voltage Transients in Digital Systems on a Chip. J Electron Test 21, 349–363 (2005). https://doi.org/10.1007/s10836-005-0972-z
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DOI: https://doi.org/10.1007/s10836-005-0972-z