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60 pW 20 μm size CMOS implementation of an actual soma membrane

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Abstract

The article presents a 65 nm technology implementation of a low-power artificial spiking neuron intellectual property (IP) core. The concept of the circuit is based on modeling the mechanism of a perikaryon membrane and the propagation of the action potential in an axon. Nerve impulses are generated using a current-controlled oscillator. Thanks to this oscillator, the circuit is implemented exclusively using metal-oxide semiconductor transistors, with the omission of capacitors. The main advantage of the presented implementation is the possibility of implementing the IP-core using nanometer digital complementary metal-oxide semiconductor technologies with the possibility of placing it within a common substrate with a digital processor. The circuit operates in weak-inversion mode with a 0.3 V power supply and does not require additional polarization voltages. The maximum frequency of impulse generation equals 2.5 kHz. The paper describes two operating modes of the circuit: a cortical mode with power consumption of 60 pW and a processing mode with power consumption of 52.2 pW. The power reduction was obtained using a circuit structure in which the power supply current consumption is reduced with the moment the circuit starts processing. The article also contains results of a process–voltage–temperature analysis.

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Authors and Affiliations

  1. Poznań University of Technology, Piotrowo 3A Street, 61-138, Poznan, Poland

    Szymon Szczęsny & Damian Huderek

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  1. Szymon Szczęsny
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  2. Damian Huderek
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Correspondence to Szymon Szczęsny.

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Szczęsny, S., Huderek, D. 60 pW 20 μm size CMOS implementation of an actual soma membrane. J Comput Electron 19, 242–252 (2020). https://doi.org/10.1007/s10825-019-01431-2

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  • DOI: https://doi.org/10.1007/s10825-019-01431-2

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