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Towards enhanced I/O performance of a highly integrated many-core processor by empirical analysis

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Abstract

Optimized for parallel operations, Intel’s second generation Xeon Phi processor, code-named Knights Landing (KNL), is actively utilized in high performance computing systems based on its highly integrated cores and high-bandwidth on-package memory, Multi-Channel DRAM (MCDRAM). Recently, the emergence of data-intensive applications and the utilization of many-core processors have further increased I/O performance requirements of high performance computing systems. Therefore, it is necessary to understand and analyze the I/O characteristics of many integrated core systems. In this paper, we experimentally analyze the I/O characteristics of KNL, focusing on single-thread, buffered-write operations. We determine that KNL has a bottleneck in its buffered write operation that utilizes page cache. To find this bottleneck point and identify its cause, we conduct the experiments in two different ways. First, we measure the execution time of kernel functions through kernel I/O path. Second, we measure the occurrence count of system events such as cache-misses and branch-misses. With results from these experiments, we discuss the characteristics on KNL’s I/O performance involving the performance bottlenecks.

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Funding

This work was supported by the Korea Institute of Science and Technology Information (K-21-L02-C08-S01), the National Supercomputing Center with supercomputing resources including technical support (KSC-2020-INO-0044), the PF Class Heterogeneous High Performance Computer Development Program (NRF-2016M3C4A7952587), the Next-Generation Information Computing Development Program (NRF-2015M3C4A7065646), the Basic Science Research Program (NRF-2020R1F1A1072696), BK21 FOUR Intelligence Computing (4199990214639, Dept. of Computer Science and Engineering, Seoul National University) through the National Research Foundation of Korea (NRF) funded by the Ministry of Science and ICT, Seoul R&D Program (CY20038) “Commercializing of technology for CAT Pro Web service based on AI” and the Technology development Program (S2878336) funded by the Ministry of SMEs and Startups (MSS, Korea)

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Authors and Affiliations

  1. Korea Aerospace University, Goyang-si, Republic of Korea

    Cheongjun Lee & Jaehwan Lee

  2. Seoul National University, Seoul, Republic of Korea

    Donghun Koo, Chungyong Kim, Jiwoo Bang & Hyeonsang Eom

  3. Korea Institute of Science and Technology Information, Daejeon, Republic of Korea

    Eun-Kyu Byun

Authors
  1. Cheongjun Lee
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  2. Jaehwan Lee
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  4. Chungyong Kim
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  7. Hyeonsang Eom
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Contributions

CL: Software, Writing—original draft, Review, Validation. JL: Conceptualization, Supervision, Writing—original draft, Funding acquisition, Project administration. DK: Software, Validation, Data curation. CK: Writing—original, Validation, Methodology. JB: Methodology, Data curation. EB: Supervision, Resources, Funding acquisition. HE: Project administration, Funding acquisition, Conceptualization.

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Correspondence to Jaehwan Lee.

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The authors declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this paper.

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Lee, C., Lee, J., Koo, D. et al. Towards enhanced I/O performance of a highly integrated many-core processor by empirical analysis. Cluster Comput 26, 2643–2655 (2023). https://doi.org/10.1007/s10586-021-03288-2

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  • DOI: https://doi.org/10.1007/s10586-021-03288-2

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