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A FHD 1080, 120 fps CMOS image sensor with two step SS-ADC

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Abstract

This paper presents a full high definition 1920 × 1080 pixel, 120 frames/s CMOS image sensor with two-step single-slope (TS-SS) ADC. The column-parallel TS-SS ADC and binary subtractor are used to convert photodiode voltage to the final 10-bit digital data. Therefore, there is no need for the pixel readout, noise suppression or comparator offset cancellation circuits to be used in the columns. A new ramp signal generator is proposed to generate 32 concurrent and identical ramp signals. TS-SS ADC improves the conversion speed while reducing the power consumption level as well. The proposed image sensor has been designed using TSMC 0.18 μm 1-poly 4-metal standard process. The simulation results show that the total comparator referred noise to the FD node in 1 Hz–100 MHz range is 0.574 mV and, also the total power consumption is about 100 mW.

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Authors and Affiliations

  1. Faculty of Electrical and Computer Engineering, University of Tabriz, Tabriz, Iran

    Masood Teymouri & Jafar Sobhi

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  1. Masood Teymouri
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  2. Jafar Sobhi
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Correspondence to Jafar Sobhi.

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Teymouri, M., Sobhi, J. A FHD 1080, 120 fps CMOS image sensor with two step SS-ADC. Analog Integr Circ Sig Process 99, 339–347 (2019). https://doi.org/10.1007/s10470-018-1349-4

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  • DOI: https://doi.org/10.1007/s10470-018-1349-4

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