Dieser Artikel beschreibt Ziele und Lösungsansatz des prämierten FIT-IT-"Embedded Systems"-Projekts "Distributed Algorithms for Robust Tick Synchronization" (DARTS), das der Entwicklung einer fehlertoleranten Alternative zur herkömmlichen Taktgenerierung in VLSI-Chips, Systems-on-Chip und anderen Hardwaresystemen gewidmet ist. Anstatt das Taktsignal eines einzelnen Oszillators mit Hilfe eines aufwändig balancierten Clock-Trees systemweit zu verteilen, wird in DARTS der Takt jeder Funktionseinheit mit Hilfe eines lokalen Taktgenerators erzeugt. Damit wird der "Single Point of Failure" eliminiert, den ein zentraler Oszillator zwangsläufig darstellt. Im Gegensatz zum klassischen "Globally Asynchronous Locally Synchronous" (GALS)-Ansatz sind die lokalen Taktgeneratoren beim DARTS-Ansatz jedoch keine Oszillatoren, sondern Instanzen eines verteilten Algorithmus zur fehlertoleranten Generierung synchronisierter lokaler Taktsignale.
This paper describes objective and rationale of the award-winning FIT-IT "Embedded Systems" Project "Distributed Algorithms for Robust Tick Synchronization" (DARTS). Within DARTS a fault-tolerant alternative to the conventional clock generation and clock distribution scheme for VLSI chips, systems-on-chip and similar hardware systems is being developed. Rather than globally distributing the clock produced by a single oscillator over an elaborately balanced clock tree, we propose to equip each functional unit with its own local clock generator. This eliminates the "single point of failure" constituted by a central clock. However, in contrast to the traditional "Globally Asynchronous Locally Synchronous" (GALS) approach DARTS does not employ oscillators as local clock generators, but rather instances of a distributed algorithm. In this way fault-tolerant generation of globally synchronized local clock signals is accomplished.
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Schmid, U., Steininger, A. & Sust, M. FIT-IT-Projekt DARTS: dezentrale fehlertolerante Taktgenerierung. Elektrotech. Inftech. 124, 3–8 (2007). https://doi.org/10.1007/s00502-006-0409-0
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DOI: https://doi.org/10.1007/s00502-006-0409-0
Schlüsselwörter
- Fehlertolerante Taktgenerierung
- Taktsynchronisation
- Fehlertoleranter verteilter Algorithmus
- VLSI Systems-on-Chip