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A Lock Detector Loop for Low-power PLL-Based Clock and Data Recovery Circuits

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Abstract

This work presents a phase-locked loop (PLL)-based clock and data recovery (CDR) circuit with a lock detector loop to reduce the voltage ripple of voltage-controlled oscillator (VCO). A tunable charge pump is used in this work to adjust the charge current depending on the state of lock detector loop, which is determined by seven clocks with equal phase difference. An experimental prototype is implemented using a typical 0.18-\(\upmu \)m CMOS process to justify the performance. The measurement results reveal that lock detector loop could reduce the voltage amplitude of Vctrl, which is the control of VCO. Notably, the voltage amplitude of Vctrl is reduced 75% from 1 V to 250 mV.

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Acknowledgements

This investigation was partially supported by National Science Council and Metal Industries Research Development Center (MIRDC) under Grant NSC102-2221-E-110-081-MY3, NSC102-2221-E-110-083-MY3, MOST104-2622-E-006-040-CC2, MOST104-ET-E-110-002-ET, MOST105-2221-E-110-058-, and MOST105-2218-E-110-006-. The authors would like to express their deepest gratefulness to Chip Implementation Center of National Applied Research Laboratories, Taiwan, for their thoughtful chip fabrication service and EDA tool support.

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Authors and Affiliations

  1. Department of Electrical Engineering, National Sun Yat-Sen University, Kaohsiung, Taiwan

    Chua-Chin Wang, Zong-You Hou & Chih-Lin Chen

  2. Department of Electrical Engineering, Tel-Aviv University, 69978, Tel-Aviv, Israel

    Doron Shmilovitz

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  1. Chua-Chin Wang
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  2. Zong-You Hou
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Correspondence to Chua-Chin Wang.

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Wang, CC., Hou, ZY., Chen, CL. et al. A Lock Detector Loop for Low-power PLL-Based Clock and Data Recovery Circuits. Circuits Syst Signal Process 37, 1692–1703 (2018). https://doi.org/10.1007/s00034-017-0621-7

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  • DOI: https://doi.org/10.1007/s00034-017-0621-7

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