[go: up one dir, main page]
More Web Proxy on the site http://driver.im/ Skip to main content
Springer Nature Link
Log in

Reducing the Dissipated Energy in Multi-standard Turbo and LDPC Decoders

  • Published:
Circuits, Systems, and Signal Processing Aims and scope Submit manuscript

Abstract

Parallel Low-Density Parity-Check and turbo code decoding consists of iterative processes that rely on the exchange of messages among multiple processing elements (PEs). They are characterized by complex communication patterns that require area expensive interconnect and memory management. Channel decoders based on Networks-on-Chip (NoCs) have been proposed in the literature, showing unmatched degrees of flexibility, but yielding high area occupation and power consumption. While general and application-specific power reduction techniques are available to save energy, the gap with respect to dedicated decoders is still large. This paper proposes techniques that reduce and optimize the traffic on the network for NoC-based channel decoders, and can be applied to any NoC architecture. The proposed techniques exploit the probabilistic nature and the processing order of the exchanged messages in the iterative decoding and define novel importance and urgency metrics. Given a target throughput, these techniques allow to consistently reduce and optimize the NoC traffic with minor or no bit error rate (BER) degradation with respect to a decoder with no traffic optimization. An already available NoC-based decoder enhanced with the proposed traffic shaping techniques leads to 13.1 % area overhead and 15.0 % power and energy reduction, while 40.2 % of power is saved on the NoC alone.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Subscribe and save

Springer+ Basic
£29.99 /Month
  • Get 10 units per month
  • Download Article/Chapter or eBook
  • 1 Unit = 1 Article or 1 Chapter
  • Cancel anytime
Subscribe now

Buy Now

Price includes VAT (United Kingdom)

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11

Similar content being viewed by others

References

  1. M. Alles, T. Vogt, N. Wehn, FlexiChaP: A reconfigurable ASIP for convolutional, turbo, and LDPC code decoding. 2008 5th International Symposium on Turbo Codes and Related Topics, pp. 84–89 (2008)

  2. E. Amador, R. Pacalet, V. Rezard, Optimum LDPC decoder: a memory architecture problem. ACM/IEEE Design Automation Conference, pp. 891–896 (2009)

  3. L.R. Bahl, J. Cocke, F. Jelinek, J. Raviv, Optimal decoding of linear codes for minimizing symbol error rate. IEEE Trans. Inf. Theory 20(3), 284–287 (1974)

    Article  MATH  MathSciNet  Google Scholar 

  4. A. Banerjee, P. Wolkotte, R. Mullins, S. Moore, G.J.M. Smit, An energy and performance exploration of network-on-chip architectures. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 17(3), 319–329 (2009)

    Article  Google Scholar 

  5. V.E. Benes, Mathematical Theory of Connecting Networks and Telephone Traffic (Academic Press, Amsterdam, 1965)

    MATH  Google Scholar 

  6. L. Benini, Application specific NoC design. Design, Automation and Test in Europe Conference and Exhibition, pp. 1330–1335 (2006)

  7. C. Condo, G. Masera, A flexible NoC-based LDPC code decoder implementation and bandwidth reduction methods. Conference on Design and Architectures for Signal and Image Processing, pp. 1–8 (2011)

  8. C. Condo, M. Martina, G. Masera, A network-on-chip-based turbo/LDPC decoder architecture. IEEE Design, Automation Test in Europe Conference Exhibition, pp. 1525–1530 (2012)

  9. C. Condo, A. Baghdadi, G. Masera, A joint communication and application simulator for NoC-based custom socs: LDPC and turbo codes parallel decoding case study. Euromicro Conference on Digital System Design, pp. 168–174 (2013)

  10. C. Condo, M. Martina, G. Masera, VLSI implementation of a multi-mode turbo/LDPC decoder architecture. IEEE Trans. Circuits Syst. I 60(6), 1441–1454 (2013)

    Article  MathSciNet  Google Scholar 

  11. Y. Cui, X. Peng, Z. Chen, X. Zhao, Y. Lu, D. Zhou, S. Goto, Ultra low power QC-LDPC decoder with high parallelism. IEEE International SOC Conference, pp. 142–145 (2011)

  12. W. Dally, Virtual-channel flow control. International Symposium on Computer Architecture, pp. 60–68 (1990)

  13. A.V. de Mello, L.C. Ost, F.G. Moraes, N.L.V. Calazans, Evaluation of routing algorithms on mesh based NoCs. Faculdade de Informatica, Pontifcia Universidade Catolica do Rio Grande do Sul, Tech. Rep, vol. 40 (2004)

  14. Digital Video Broadcasting (DVB); Interaction channel for Satellite Distribution Systems. ETSI Std. TR 101 790 V1.I. (2005)

  15. R.G. Gallager, Low density parity check codes. IRE Trans. Inf. Theory IT 8(1), 21–28 (1962)

    Article  MATH  MathSciNet  Google Scholar 

  16. G. Gentile, M. Rovini, L. Fanucci, A multi-standard flexible turbo/LDPC decoder via ASIC design. International Symposium on Turbo Codes & Iterative Information Processing, pp. 294–298 (2010)

  17. D. Hocevar, A reduced complexity decoder architecture via layered decoding of LDPC codes. IEEE Workshop on Signal Processing Systems, pp. 107–112 (2004)

  18. Homeplug AV Specification. Homeplug Alliance Std. (2005)

  19. W.H. Hu, J.H. Bahn, N. Bagherzadeh, Parallel LDPC decoding on a Network-on-Chip based multiprocessor platform. International Symposium on Computer Architecture and High, Performance Computing, pp. 35–40 (2009)

  20. W. Hung, C. Addo-Quaye, T. Theocharides, Y. Xie, N. Vijakrishnan, M. Irwin, Thermal-aware IP virtualization and placement for networks-on-chip architecture. IEEE International Conference on Computer Design: VLSI in Computers and Processors, pp. 430–437 (2004)

  21. A. Hunt, S. Crozier, K. Gracie, P. Guinand, A completely safe early-stopping criterion for max-log turbo code decoding. International Symposium on Turbo Codes and Related Topics, pp. 1–6 (2006)

  22. IEEE Standard for Local and Metropolitan Area Networks Part 16: Air Interface for Fixed and Mobile Broadband Wireless. IEEE Std 802.16e-2005 Std. (2006)

  23. IEEE Standard for Information technology-Telecommunications and information exchange between systems-Local and metropolitan area networks. IEEE Std 802.11n-2009 Std. (2009)

  24. M. Imase, M. Itoh, A design for directed graphs with minimum diameter. IEEE Trans. Comput. C 32(8), 782–784 (1983)

    Article  MATH  Google Scholar 

  25. J. Li, X.H. You, J. Li, Early stopping for LDPC decoding: convergence of mean magnitude (CMM). IEEE Commun. Lett. 10(9), 667–669 (2006)

    Article  MathSciNet  Google Scholar 

  26. S.H. Lo, Y.C. Lan, H.H. Yeh, W.C. Tsai, Y.H. Hu, S.J. Chen, QoS aware BiNoC architecture. IEEE International Symposium on Parallel Distributed Processing, pp. 1–10 (2010)

  27. M. Martina, G. Masera, A framework for the design of Network-on-Chip-based turbo decoder architectures. IEEE Trans. Circuits Syst. I 57(10), 2776–2789 (2010)

    Article  MathSciNet  Google Scholar 

  28. H. Moussa, A. Baghdadi, M. Jezequel, Binary de Bruijn interconnection network for a flexible LDPC/turbo decoder. IEEE International Symposium on Circuits and Systems, pp. 97–100 (2008)

  29. H. Moussa, A. Baghdadi, M. Jezequel, Binary De Bruijn onchip network for a flexible multiprocessor LDPC decoder. ACM/IEEE Design Automation Conference, pp. 429–434 (2008)

  30. O. Muller, A. Baghdadi, M. Jezequel, Bandwidth reduction of extrinsic information exchange in turbo decoding. IET Electron. Lett. 42(19), 1104–1105 (2006)

    Article  Google Scholar 

  31. Multiplexing and Channel Coding. 3GPP Std. TS36.212 (2012)

  32. C. Neeb, M. Thul, N. Wehn, Network-on-chip-centric approach to interleaving in high throughput channel decoders. IEEE International Symposium on Circuits and Systems, pp. 1766–1769 Vol. 2 (2005)

  33. M. Rovini, G. Gentile, F. Rossi, L. Fanucci, A scalable decoder architecture for IEEE 802.11n LDPC codes. IEEE Global Telecommunications Conference, pp. 3270–3274 (2007)

  34. C. Studer, C. Benkeser, S. Belfanti, Q. Huang, Design and implementation of a parallel turbo-decoder ASIC for 3GPP-LTE. IEEE J. Solid State Circuits 46(1), 8–17 (2011)

    Article  Google Scholar 

  35. P. Urard, L. Paumier, M. Viollet, E. Lantreibecq, H. Michel, S. Muroor, B. Coates, B. Gupta, A generic 350 Mb/s turbo-codec based on a 16-states SISO decoder. IEEE International Solid-State Circuits Conference, pp. 424–536, Vol. 1 (2004)

  36. F. Vacca, H. Moussa, A. Baghdadi, G. Masera, Flexible architectures for LDPC decoders based on network on chip paradigm. Euromicro Conference on Digital System Design, pp. 582–589 (2009)

Download references

Author information

Authors and Affiliations

  1. Politecnico di Torino, Corso Duca degli Abruzzi 24, 10129, Torino, Italy

    Carlo Condo & Guido Masera

  2. Telecom Bretagne, Technopole Brest-Iroise, 29238, Brest Cedex 3, France

    Amer Baghdadi

Authors
  1. Carlo Condo
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Amer Baghdadi
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Guido Masera
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Carlo Condo.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Condo, C., Baghdadi, A. & Masera, G. Reducing the Dissipated Energy in Multi-standard Turbo and LDPC Decoders. Circuits Syst Signal Process 34, 1571–1593 (2015). https://doi.org/10.1007/s00034-014-9915-1

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s00034-014-9915-1

Keywords

Search

Navigation