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Design of a viterbi decoder with microprocessor-based serial implementation

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Applicable Algebra, Error-Correcting Codes, Combinatorics and Computer Algebra (AAECC 1986)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 307))

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Abstract

The purpose of this paper is to present the design of a Viterbi decoder, for moderate data transmission rates (hundreds of bits/sec), using a serial implementation based on a 16/32-bit microprocessor.

This design is only one experimental phase of a final version which will be constructed to operate at a data transmission rate of 32 Kbits/sec, utilizing principally MECL and TTL integrated circuits.

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References

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Author information

Authors and Affiliations

  1. División de Estudios de Posgrado Facultad de Ingeniería, UNAM, Cd. Universitaria, A.P. 70-256, 04510, MEXICO, DF

    F. J. García-Ugalde & R. H. Morelos-Zaragoza A

Authors
  1. F. J. García-Ugalde
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  2. R. H. Morelos-Zaragoza A
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Thomas Beth Michael Clausen

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© 1988 Springer-Verlag Berlin Heidelberg

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García-Ugalde, F.J., Morelos-Zaragoza A, R.H. (1988). Design of a viterbi decoder with microprocessor-based serial implementation. In: Beth, T., Clausen, M. (eds) Applicable Algebra, Error-Correcting Codes, Combinatorics and Computer Algebra. AAECC 1986. Lecture Notes in Computer Science, vol 307. Springer, Berlin, Heidelberg. https://doi.org/10.1007/BFb0039179

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  • DOI: https://doi.org/10.1007/BFb0039179

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-19200-8

  • Online ISBN: 978-3-540-39133-3

  • eBook Packages: Springer Book Archive

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