Abstract
Software pipelining is an effective technique for increasing the throughput of loops in superscalar or VLIW machines, however it generates high register pressure, which in some cases requires the introduction of spill code into the schedule. Large multi-ported register files present significant problems in the construction of scalable VLIW systems, which has lead us to investigate architectures in which part of the register file is replaced by queues. We believe that this organization has distinct advantages in terms of hardware complexity, silicon area, instruction name space, and scalability. Queues also represent a natural mechanism for communication between clusters of functional units in a partitioned VLIW system. In this paper we present an overview of this approach, along with some experimental results suggesting it as being a feasible organization.
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© 1997 Springer-Verlag Berlin Heidelberg
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Fernandes, M.M., Llosa, J., Topham, N. (1997). Allocating lifetimes to queues in software pipelined architectures. In: Lengauer, C., Griebl, M., Gorlatch, S. (eds) Euro-Par'97 Parallel Processing. Euro-Par 1997. Lecture Notes in Computer Science, vol 1300. Springer, Berlin, Heidelberg. https://doi.org/10.1007/BFb0002854
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DOI: https://doi.org/10.1007/BFb0002854
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