[go: up one dir, main page]
More Web Proxy on the site http://driver.im/ Skip to main content
Log in

The pin redistribution problem in multi-chip modules

  • Published:
Mathematical Programming Submit manuscript

    We’re sorry, something doesn't seem to be working properly.

    Please try refreshing the page. If that doesn't work, please contact support so we can address the problem.

Abstract

We introduce thepin redistribution problem (PRP), which arises from layout design ofmulti-chip modules. The problem is to redistribute the pins uniformly over the MCM substrate using a number of pin redistribution layers.

Pin redistribution is very important in MCM design because it has been used to not only provide a minimum spacing between signal wires in dense signal distribution layers, but also provide engineering change capability [3, 4]. Moreover, our experience [10] showed that the capacitive coupling noise between vias (one of the major problems in designing MCMs) induced by many layers (up to 63 layers) can be reduced using the pin redistribution technique.

The goal of the problem is to minimize the number of layers required to redistribute the entire set. As a net is undefined, a number of challenging issues arise. Three effective approaches are proposed for solving this problem.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Subscribe and save

Springer+ Basic
£29.99 /Month
  • Get 10 units per month
  • Download Article/Chapter or eBook
  • 1 Unit = 1 Article or 1 Chapter
  • Cancel anytime
Subscribe now

Buy Now

Price includes VAT (United Kingdom)

Instant access to the full article PDF.

Similar content being viewed by others

References

  1. H.B. Bakoglu,Circuits, Interconnections, and Packaging for VLSI (Addison-Wesley, Reading, MA, 1990) pp. 81–112.

    Google Scholar 

  2. J.L. Bentley and T. Ottmann, “Algorithm for reporting and counting Geometric Intersections,”IEEE Transactions on Computer C-28 (1979) 643–647.

    Google Scholar 

  3. A.J. Blodgett, “Microelectronic Packaging,”Scientific American (1983) 86–96.

  4. A.J. Blodgett and D.R. Barbour, “Thermal conduction module: A high performance multilayer ceramic package,”IBM Journal of Research and Development 26(1) (1982) 30–36.

    Google Scholar 

  5. M.L. Brady and D.J. Brown, “VLSI routing: Four layers suffice,” in: F.P. Preparata, ed.,VLSI Theory No. 2. Advances in Computing Research (JAI Press, Greenwich, CT, 1984) pp. 245–257.

    Google Scholar 

  6. M. Burstein and R. Pelavin, “Hierarchical wire routing,”IEEE Transactions on Computer Aided Design CAD-2(4) (1983) 223–234.

    Google Scholar 

  7. R.C. Carden IV and C.K. Cheng, “A global router using an efficient approximate multicommodity multiterminal flow algorithm,” in:Design Automation Conference (IEEE/ACM, 1991) pp. 316–321.

  8. B. Chazelle, “An algorithm for segment-dragging and its implementation,”Algorithmica 3 (1988) 205–221.

    Google Scholar 

  9. C. Chiang, M. Sarrafzadeh and C.K. Wong, “A global router with simultaneous length and density minimization,” Manuscript (June 1991).

  10. J.D. Cho, K.F. Liao and M. Sarrafzadeh, “Multilayer routing algorithm for high performance MCMs,” in:Proceedings of the Fifth Annual IEEE International ASIC Conference and Exhibit (1992) pp. 226–229; also to appear in:IEEE Transactions on Circuits and Systems (1994).

  11. W. Wei-Ming Dai, “Performance driven layout of thin-film substrates for multichip modules,” in:Proceedings of Multichip Module Workshop (IEEE, 1990) pp. 114–121.

  12. H.C. Du and K.C. Chang, “A new approach for layer assignment problem,” in: Technical Report TR-84-20, Computer Science Department, University of Minnesota (Minneapolis, MN, 1984).

    Google Scholar 

  13. P.D. Franzon, Private communication, Electronic MCM Clearing House in North Carolina State University (Raleigh, NC, 1992).

  14. J.M. Ho, M. Sarrafzadeh, G. Vijayan and C.K. Wong, “Layer assignment for multi-chip modules,”IEEE Transactions on Computer Aided Design, CAD-9(12) (1990) 1272–1277.

    Google Scholar 

  15. T.C. Hu and M.T. Shing, “A decomposition algorithm for circuit routing,”Mathematical Programming Study 24 (1985) 87–103.

    Google Scholar 

  16. L.-T. Hwang, D. Nayak, I. Turlik and A. Reisman, “Thin-film pulse propagation analysis using frequency techniques,”IEEE Transactions on CHMT 14 (1991).

  17. L.-T. Hwang and I. Turlik, “The skin effect in thin-film interconnections for ULSI/VLSI packages,” MCNC Technical Reports, Technical Report Series TR91-13 (1991).

  18. R.M. Karp, F.T. Leighton, R.L. Rivest, C.D. Thompson, U.V. Vazirani and V.V. Vazirani, “Global wire routing in two-dimensional arrays,”Algorithmica 2(1) (1987) 113–129.

    Google Scholar 

  19. S. Kirkpatrick, C.D. Gelatt Jr. and M.P. Vecchi, “Optimization by simulated annealing,”Science 220 (1983) 671–680.

    Google Scholar 

  20. D. König,Theorie der Endlichen und Unendlichen Graphen. (Leipzig, 1936; reprinted: Chelsea, 1950).

  21. E.S. Kuh and M. Marek-Sadowska, “Global routing,” in: T. Ohtsuki, ed.,Layout Design and Verification. Advances in CAD for VLSI No. 4 (Elsevier, Science Amsterdam, 1986).

    Google Scholar 

  22. E.S. Kuh and T. Outsuki, “Recent advances in VLSI layout,” in:Proceedings of the IEEE (1990) pp. 250–251.

  23. C.Y. Lee, “An algorithm for path connection and its application”,IRE Transaction on Electronic Computer EC-10 (1961) 346–365.

  24. D.T. Lee, S.J. Hong and C.K. Wong, “Number of vias: A control parameter for global wiring of highdensity chips,”IBM Journal of Research and Development 25(4) (1981) 261–271.

    Google Scholar 

  25. T. Lengauer,Combinatorial Algorithms for Integrated Circuit Layout (Wiley, New York, 1990) Chapter 9.

    Google Scholar 

  26. J.T. Li and M. Marek-Sadowska, “Global routing for gate arrays,”IEEE Transactions on Computer Aided Design CAD-3(4) (1984) 298–307.

    Google Scholar 

  27. K.F. Liao, M. Sarrafzadeh and C.K. Wong, “Single-layer global routing,” in:Proceedings of the Fourth Annual IEEE International ASIC Conference and Exhibit (IEEE, September 1991. New York, 1991) pp. 14-4.1–14-4.4; also to appear in:IEEE Transactions on Computer Aided Design (1993).

    Google Scholar 

  28. W.K. Luk, P. Sipala, M. Tamminen, D. Tang, L.S. Woo and C.K. Wong, “A hierarchical global wiring algorithm for custom chip design,”IEEE Transactions on Computer Aided Design CAD-6(4) (1987) 518–533.

    Google Scholar 

  29. M. Marek-Sadowska, “Route planner for custom chip design,” in:International Conference on Computer-Aided Design (IEEE, 1986) pp. 246–249.

  30. G. Meixner and U. Lauther, “A new global router based on a flow model and linear assignment,” in:International Conference on Computer-Aided Design (IEEE, New York, 1990) pp. 44–47.

    Google Scholar 

  31. P, Molitor, “A survey on wiring,”Journal of Information Processes in Cybernetics EIK 27 1 (1991) 3–19.

    Google Scholar 

  32. R. Nair, “A simple yet effective technique for global wiring,”IEEE Transactions on Computer Aided Design CAD-6(2) (1987) 165–172.

    Google Scholar 

  33. Y. Nishizaki, M. Igusa and A. Sangiovanni-Vincentelli, “Mercury: A new approach to macro-cell global routing,” in:Proceedings of VLSI, Germany (1989) pp. 411–419.

  34. C.H. Papadimitriou and K. Steiglitz, “Weighted matching,” in:Combinatorial Optimization (Prentice-Hall, Englewood Cliffs, NJ, 1982) pp. 247–270.

    Google Scholar 

  35. K. Patron, “An algorithm for finding a fundamental set of cycles of a graph,”Communications of the ACM 9(9) (1969) 514–518.

    Google Scholar 

  36. B. Preas, M. Pedram and D. Curry, “Automatic layout of silicon-on-silicon hybrid packages,” in:Design Automation Conference (1989) 394–399.

  37. M. Sarrafzadeh and D. Zhou, “Global routing of short nets in two-dimensional arrays,”The International Journal of Computer Aided VLSI Design 2(2) (1990) 197–211.

    Google Scholar 

  38. E. Shargowitz and J. Keel, “A global router based on multicommodity flow model,”INTEGRATION: The VLSI Journal 5 (1987) 3–16.

    Google Scholar 

  39. J. Soukup, “Global router,” in:25 Years of Electronic Design Automation, 1988 (1979) pp. 206–209.

  40. M.P. Vecchi and S. Kirkpatrick, “Global wiring by simulated annealing,”IEEE Transactions on Computer Aided Design CAD-2(4) (1983) 215–222.

    Google Scholar 

  41. H.Y. Youn and A.D. Singh, “An efficient channel routing algorithm for defective arrays,” in:International Conference on Computer-Aided Design (IEEE, 1989) pp. 432–435.

Download references

Author information

Authors and Affiliations

Authors

Additional information

This work was supported in part by the National Science Foundation under Grant MIP-8921540.

This author was supported in part by a Samsung Electronics Fellowship.

A preliminary version of this paper appeared in theProceedings of the Fourth Annual IEEE International ASIC Conference and Exhibit, September 1991, pp. 9-2.1–9-2.4.

Rights and permissions

Reprints and permissions

About this article

Cite this article

Cho, J.D., Sarrafzadeh, M. The pin redistribution problem in multi-chip modules. Mathematical Programming 63, 297–330 (1994). https://doi.org/10.1007/BF01582074

Download citation

  • Received:

  • Revised:

  • Issue Date:

  • DOI: https://doi.org/10.1007/BF01582074

Keywords

Navigation