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Bit-Level systolic architectures for high performance IIR filtering

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Abstract

Several novel systolic architectures for implementing densely pipelined bit parallel IIR filter sections are presented. The fundamental problem of latency in the feedback loop is overcome by employing redundant arithmetic in combination with bit-level feedback, allowing a basic first-order section to achieve a wordlength-independent latency of only two clock cycles. This is extended to produce a building block from which higher order sections can be constructed. The architecture is then refined by combining the use of both conventional and redundant arithmetic, resulting in two new structures offering substantial hardware savings over the original design. In contrast to alternative techniques, bit-level pipelinability is achieved with no net cost in hardware.

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Authors and Affiliations

  1. Signal Processing Group, Royal Signals and Radar Establishment, Saint Andrews Road, Great Malvern, Worcestershire, England

    S. C. Knowles & J. G. McWhirter

  2. Department of Electrical and Electronic Engineering, The Queen's University, Stranmillis Road, Belfast, Northern Ireland

    R. F. Woods & J. V. McCanny

Authors
  1. S. C. Knowles
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  2. J. G. McWhirter
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  3. R. F. Woods
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  4. J. V. McCanny
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Knowles, S.C., McWhirter, J.G., Woods, R.F. et al. Bit-Level systolic architectures for high performance IIR filtering. J VLSI Sign Process Syst Sign Image Video Technol 1, 9–24 (1989). https://doi.org/10.1007/BF00932062

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  • DOI: https://doi.org/10.1007/BF00932062

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