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Dynamic programming implementation on array processor architectures

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Abstract

Dynamic Programming (DP) applies to many signal and image processing applications including boundary following, the Viterbi algorithm, dynamic time warping, etc. This paper presents an array processor implementation of generic dynamic programming. Our architecture is a SIMD array attached to a host computer. The processing element of the architecture is based on an ASIC design opting for maximum speed-up. By adopting a torus interconnection network, a dual buffer structure, and a multilevel pipeline, the performance of the DP chip is expected to reach the order of several GOPS. The paper discusses both the dedicated hardware design and the data flow control of the DP chip and the total array.

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References

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Authors and Affiliations

  1. Department of Electrical and Computer Engineering, Aristotle University of Thessaloniki, GR-54006, Thessaloniki, Greece

    K. I. Diamantaras

  2. Auspy Development Inc., 10430 S. De Anza Blvd., Suite 275, 95014, Cupertino, CA

    W. H. Chou

  3. Department of Electrical Engineering, 08544, Princeton, NJ, USA

    S. Y. Kung

Authors
  1. K. I. Diamantaras
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  2. W. H. Chou
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  3. S. Y. Kung
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Additional information

This work was supported in part by the NATO, Scientific and Environmental Affairs Division, Collaborative Research Grant SA.5-2-05(CRG.960201)424/96/JARC-501.

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Diamantaras, K.I., Chou, W.H. & Kung, S.Y. Dynamic programming implementation on array processor architectures. J VLSI Sign Process Syst Sign Image Video Technol 13, 27–35 (1996). https://doi.org/10.1007/BF00930665

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  • DOI: https://doi.org/10.1007/BF00930665

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