[go: up one dir, main page]
More Web Proxy on the site http://driver.im/ Skip to main content

Advertisement

Springer Nature Link
Log in

Challenges in advanced semiconductor technology for high-performance and supercomputer applications

  • Published:
The Journal of Supercomputing Aims and scope Submit manuscript

Abstract

This article provides a review of the capabilities, future directions, and technology challenges for semiconductor chips and packages as they apply to high-performance and supercomputer applications. Semiconductor chip technology has resulted in dramatic device density improvements over the last 20 years. Scaling theory predicts that continued improvements will be possible if the technological problems associated with patterning, doping, interconnection, density, yield, and cost can be solved. The issues associated with these challenges are discussed. Finally, the packaging needs to support advanced chip technologies are reviewed.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Subscribe and save

Springer+ Basic
£29.99 /Month
  • Get 10 units per month
  • Download Article/Chapter or eBook
  • 1 Unit = 1 Article or 1 Chapter
  • Cancel anytime
Subscribe now

Buy Now

Price includes VAT (United Kingdom)

Instant access to the full article PDF.

Institutional subscriptions

Similar content being viewed by others

References

  1. Reisman, A. 1983. Device, circuit, and technology scaling to micron and submicron dimensions. Proc. IEEE, 71, 550.

    Google Scholar 

  2. Reisman, A. 1982. The technology and engineering challenges posed by very large scale integration. Proc. of the Tutorial Symp. on Semiconductor Technology, Electrochemical Society Proceedings, 82–5, 221.

    Google Scholar 

  3. Tang, D. D., and Ning, T. H. 1985. Advances in bipolar IC technology. IEEE 1985 CICC, 180.

  4. U.S. midyear market report. 1986. Electronics, 105 (July 10).

  5. Holton, W. C., and Cavin, R. K., III. 1986. A perspective on CMOS technology trends. IEEE, to be published.

  6. Takayama, Y., Fujii, S., Tanabe, T., Kawauchi, K., Yoshida, T., and Yamashita, K. 1985. A 1ns 20K CMOS gate array series with configurable 15ns 12K memory. ISSCC Digest of Technical Papers, 196.

  7. Takahashi, H., Sato, S., Goto, G., and Nakamura, T. 1985. A 240K transistor CMOS array with flexible allocation of memory and channels. ISSCC Digest of Technical Papers, 124.

  8. Sakashita, K., Arakawa, T., Takagi, H., Sugizaka K., Asai, S., and Ohkura, I. 1983. A 10K gate CMOS gate array with gate isolation configurations. CICC, 14.

  9. Nishimura, T., Matsumoto, K., Kudo, O., Muryama, M., Ooka, H., Koyata, K., and Tsubokura, F. 1984. An advanced 11K gate CMOS gate array with fully automated design system. CICC, 210.

  10. Saigo, T., Niwa, K., Ohto, T., Kurosawa, S., and Takada, T. 1985. A triple-level wired 24K gate CMOS gate array. ISSCC Digest of Technical Papers, 122.

  11. Takechi, M., Ikuzaki, K., Itoh, T., and Fujita, M. 1984. A CMOS 12K gate array with flexible 10Kb memory. ISSCC Digest of Technical Papers, 258.

  12. Yamagishi, M., Takechi, M., Ikuzaki, K., Fujita, M., Murata, S., Nogami, K., Asano, M., and Masaki, A. 1985. A subnanosecond 18K-gate CMOS gate array with 4.6K-bit-on-chip RAM. Proc. IEEE Intl. Conf. on Computer Design, 25.

  13. Sporck, F. R., Rideout, V. L., Piro, R. A., and Tom, S. 1984. A CMOS masterslice chip with versatile design features. CICC, 192.

  14. Swartzlander, E. E. Jr., Young, W. K. W., and Joseph, S. J. 1984. A VLSI delay commutator for FFT implementation. ISSCC Digest of Technical Papers, 226.

  15. Walker, R., Yin, P., Lobo, K., Chang, Y., Tsao, P., Yuen, A., and Hsue, J. 1985. Structured arrays—a new ASIC concept provides the best of gate arrays and cell based custom. CICC, 252.

  16. Wong, T., Hui, A., Wong, D., Kobayashi, T., Suzuki, H., and Yamasaki, K. 1986. A high performance 129K gate CMOS array. CICC, 568.

  17. Gagliardi, M. P. 1984. A 13.5K CMOS gate array with 2300 dedicated analog transistors and 200 multifunctional I/O cells. CICC, 206.

  18. LeClair, K., Bell, R., Breid, D., Torgenson, P., Fier, D., and Johnson, B. 1984. A 32 bit CMOS microprocessor using a semicustom cell library. CICC, 10.

  19. Baran, D., and Bondurant, D. 1986. HC2000: a fast 20K gate array with built-in self test and system fault isolation capabilities. CICC, 315.

  20. Perner, F., Roylance, L., and Van Bree, K. 1984. Design features of a 10K CMOS gate array. CICC, 188.

  21. Arakawa, T., Ueda, M., Saito, Y., Fujimura, T., Asai, S., Terai, M., Akasaka, Y., and Kuramitsu, Y. 1986. A basic-cell buffer 440K-transistor CMOS masterslice. ISSCC Digest of Technical Papers, 78.

  22. Kuramitsu, Y., Sato, K., Akasaka, Y., and Ohkura, I. 1986. A 540K-transistor CMOS variable track masterslice. CICC, 572.

  23. Ulrich, H., Brackelmann, W., Fritzsche, H., and Wieder, A. 1985. A 100ps 9K gate ECL masterslice. ISSCC Digest of Technical Papers, 200.

  24. Horiguchi, S., Suzuki, M., Ichino, H., Konaka, S., and Sakai, T. 1985. An 80ps 2500-gate bipolar macrocell array. ISSCC Digest of Technical Papers, 198.

  25. Ichino, H., Suzuki, M., Konaka, S., and Yamamoto, E. 1986. A 50ps 7K-gate masterslice using mixed-cells consisting of an NTL gate and an LCML macrocell. CICC, 580.

  26. Larson, B. 1985. Progress in submicron bipolar technology. SRC Technology Assessment Workshop, Research Triangle Park, N.C., June 26–27.

    Google Scholar 

  27. Nishimura, T., Kato, S., Tatsuki, M., Sato, H., Kohara, M., Sakaue, K., Hirao, T., Kuramitsu, Y. 1986. A bipolar 18K gate variable-size cell masterslice. ISSCC Digest of Technical Papers, 76.

  28. 1983. ISSCC Digest of Technical Papers, 152.

  29. 1986. Density tripled in ECL gate arrays. Electronics, 90 (Jan. 6).

  30. Morkoc, H., and Solomon, P. M. 1984, The HEMT: a superfast transistor. IEEE Spectrum, 25, 2, 28.

    Google Scholar 

  31. Solomon, P. M. 1983. A comparison of semiconductor devices for high speed logic. IEEE Proceedings, 71, 550.

    Google Scholar 

  32. Hirayama, H., Furutuska, T., Tanaka, Y., Kaga, M., Kanamori, M., Takahashi, K., Kohzu, H., and Higashisaka, A. 1986. A CML compatible GaAs gate array. ISSCC Digest of Technical Papers, 72.

  33. Yuan, H.-T., Delaney, J., Shin, H. -D., and Tran, L. T. 1986. A 4K GaAs bipolar gate array. ISSCC Digest of Technical Papers, 74.

  34. Watanabe, Y., Kajii, K., Nishiuchi, K., Suzuki, M., Hanyu, I., Kosugi, M., Odani, K., Shibatomi, A., Mimura, T., Abe, M., Kobayashi, M. 1986 A high electron mobility transistor 1.5K gate array. ISSCC Digest of Technical Papers, 80.

  35. Peczalski, A., Lee, G., Betten, W., Somal, H., Vu, T., Hanka, S., Novak, R., Lee, G.Y., Gilbert, B., Naused, B., Karwoski, S. 1986. The design and performance of a GaAs 2K gate array. CICC, 517.

  36. Toyoda, N., Uchitomi, N., Kitaura, Y., Mochizuki, M., Kanazawa, K., Terada, T., Ikawa, Y., and Hojo, A. 1986. A 42ps 2K-GaAs gate array. ISSCC Digest of Technical Papers, 206.

  37. Yamaguchi, K., Kanetani, K., Todokoro, H., Nakano, T., Akimoto, K., and Ogiue, K. 1984. An ECL4K-bit bipolar RAM with an effective access time of 2.5ns. ISSCC Digest of Technical Papers, 52.

  38. Yamaguchi, K., Nambu, H., Kanetani, K., Houma, N., Nishioka, Y., Uchida, A., and Ogiue, K. 1986. A3.5ns, 2W, 20 μm2 16Kb ECL bipolar RAM. ISSCC Digest of Technical Papers, 214.

  39. Ogiue, K., Odeka, M., Miyaoka, S., Masuda, I., Ikeda, T., Tonomura, K., and Ohba, T. 1986. A 13ns/500mW 64Kb ECL RAM. ISSCC Digest of Technical Papers, 212.

  40. Miyanaga, H., Kobayashi, Y., Konaka, S., Yamamoto, Y., and Sakai, T. 1984. A 1.1ns access time 4KB bipolar RAM using super self-aligned technology. ISSCC Digest of Technical Papers, 50.

  41. Sugo, Y., Tanaka, M., Mafune, Y., Takeshima, T., Aihara, S., and Tanaka, T. 1986. An ECL 2.8ns 16K RAM with 1.2K logic gate array. ISSCC Digest of Technical Papers, 256.

  42. Okajima, Y., Toyoda, K., Awaya, T., Tanaka, K., and Nakamura, Y. 1985. 64Kb ECL RAM with redundancy. ISSCC Digest of Technical Papers, 48.

  43. Arimura, M., Nakame, M., Tashiro, T., Ohi, S., Kamiya, T., Kishi, S., Minato, Y., Nokubo, J., and Tamura, T. 1986. A 4ns access time 4K × 4 ECL RAM. ISSCC Digest of Technical Papers, 254.

  44. Chan, Y. H., Brown, J. L., Nijhuis, R. H., Rivadeneira, C. R., and Struk, J. R. 1986. A 3ns 32K bipolar RAM. ISSCC Digest of Technical Papers, 210.

  45. Heald, R., Herndon, W., Wu, I.-N., Shen, and S.-Y. 1985. A 15ns 64K bipolar SRAM. ISSCC Digest of Technical Papers, 50.

  46. Sakai, T., Miyanaga, H., Konaka, S., and Yamamoato, Y. 1984. A 0.85ns 1Kb bipolar RAM. Int. Conf. Solid-State Devices and Materials, Dig. of Tech. Papers, 225, Kobe, Japan.

  47. Minato, O., Masuhara, T., Sasaki, T., Sakai, Y., and Hayashida, T. 1984. A 20ns 64K CMOS SRAM. ISSCC Digest of Technical Papers, 222.

  48. Yamamoto, S., Uchibori, K., Nagasawa, K., Meguro, S., Yasui, T., Minato, O., and Masuhara, T. 1985. A 256K CMOS SRAM with variable-impedance loads. ISSCC Digest of Technical Papers, 58.

  49. Ozawa, T., Koshimaru, S., Kudo, O., Itoh, H., Harashima, N., Yasuoka, N., Asai, H., Yamanaka, T., and Kikuchi, S. 1984. A 25ns 64K SRAM. ISSCC Digest of Technical Papers, 218.

  50. Isobe, M., Matsunaga, J., Sakuri, T., Ohtani, T., Sawada, K., Nozawa, H., Iizuka, T., and Kohyama, S. 1984. A 46ns CMOS RAM. ISSCC Digest of Technical Papers, 214.

  51. Honda, M., Kondou, K., Mitani, H., Kimura, T., Koshimara, S., Nagahashi, Y., and Tameda, M. 1986. A 25Ichinose, Kns 256K CMOS SRAM. ISSCC Digest of Technical Papers, 250.

  52. Kohno, Y., Shinohara, H., Kawai, Y., Akasaka, Y., and Kayano, S. 1986. 25ns 256K × 1/64K × 4 CMOS SRAM. ISSCC Digest of Technical Papers, 248.

  53. Ochii, K., Yasuda, H., Kobayashi, K., Kondoh, T., and Masuoka, F. 1985. A 17ns 64K CMOS RAM with a Schmitt Trigger Sense Amplifier. ISSCC Digest of Technical Papers, 64.

  54. Segawa, M., Ariizuma, S., Suzuki, Y., Kondo, T., Ando, T., Ochii, K., and Masuoka, F. 1986. A 18ns 8KW × 9b NMOS SRAM. ISSCC Digest of Technical Papers, 202.

  55. Isobe, M., Matsunaga, J., Sakurai, T., Ohtani, T., Sawada, K., Nozawa, H., Iizuka, T., and Kohyama, S. 1984. A 46ns 256K CMOS RAM. ISSCC Digest of Technical Papers, 214.

  56. Sakuari, T., Sawada, K., Nogami, K., Wada, T., Isobe, M., Kahuma, M., Morita, S., Yokogawa, S., Kinugawa, M., Asami, T., Hashimoto, K., Matsunagaa, J.-I., Nozawa, H., and Iizuka, T. 1986. A 1Mb virtually SRAM. ISSCC Digest of Technical Papers, 252.

  57. Okazaki, N., Miyaji, F., Kobayashi, K., Harada, Y., Aoyama, J., and Shimada, T. 1986. A 30ns 256K Full CMOS SRAM. ISSCC Digest of Technical Papers, 204.

  58. Schuster, S. E., Chappel, B. A., Franch, R. L., Grier, P. F., Klepner, S. P., and Lai, J. F. S. 1986. A 15ns CMOS 64K RAM. ISSCC Digest of Technical Papers, 206.

  59. Flannagan, S. T., Reed, P. A., Voss, P., Nogle, S., Simon, S., Sheng, D., Kung, R., and Barnes, J. J. 1986. Two 64K CMOS SRAMs with 13ns access time. ISSCC Digest of Technical Papers, 208.

  60. Dennard, R. H. 1968. U.S. Patent 3 387 286 (July 4).

  61. Takemae, Y., Ema, T., Nakano, M., Baba, F. Yabu, T., Miyasaka, K., and Shiri, K. 1985. A 1Mb DRAM with 3-dimensional stacked capacitor cells. ISSCC Digest of Technical Papers, 250.

  62. Sato, Kawamoto, H., Yanagisawa, K., Matsumoto, T., Shimizu, S., and Hori, R. 1985. A 20ns static column 1Mb DRAM in CMOS technology. ISSCC Digest of Technical Papers, 254.

  63. Itoh, K., Hori, R., Eton, J., Asai, A., Hashimoto, N., Yagi, K., andSunami, H. 1984. An experimental 1Mb DRAM with on-chip voltage limiter. ISSCC Digest of Technical Papers, 282.

  64. Kumanoya, M., Fujishima, K., Tsukamoto, K., Nishimura, Y., Saito, K., Matsukawa, T., Yoshihara, T., and Nakano, T. 1985. A 90ns 1Mb DRAM with multi-bit test mode. ISSCC Digest of Technical Papers, 240.

  65. Inoue, Y., Murotani, T., Fukuzoh, Y., Hayano, K., Fujii, T., Minami, K., Nakamura, K., and Kikuchi, M. 1985. An 85ns 1Mb DRAM in a plastic DIP. ISSCC Digest of Technical Papers, 238.

  66. Fujii, S., Saito, S., Okada, Y., Sato, M., Sawada, S., Shinozake, S., Natori, K., and Ozawa, O. 1986. A 50 uA standby 1MW × 1b/256KW × 4b CMOS RAM. ISSCC Digest of Technical Papers, 266.

  67. Horiguchi, F., Itoh, Y., Iizuke, H., Ogura, M., and Masuoka, F. 1985. A 1Mb DRAM with a folded capacitor cell. ISSCC Digest of Technical Papers, 244.

  68. Kalter, H. L., Coppens, P., Ellis, W., Fifield, J., Kokoszka, D., Leasure, T., Miller, C., Nguyen, Q., Papritz, R., Patton, C., Poplawski, M., Tomashot, S., and van der Hoeven, V. 1985. An experimental 80ns 1Mb DRAM with fast page operation. ISSCC Digest of Technical Papers, 248.

  69. Kirsch, H. C., Clemons, D. G., Davar, S., Harman, J. E., Holder, C. H. Jr., Hunsicker, W. F., Procyk, F. J., Strfany, J. H., Yaney, D. S., and Petrizzi, J. B. 1985. A 1Mb CMOS DRAM. ISSCC Digest of Technical Papers, 256.

  70. Neal, J., Holland, B., Inoue, S., Loh, W. K., McAdams, H., and Poteet, K. 1986. A 1Mb CMOS DRAM with design-for-test functions. ISSCC Digest of Technical Papers, 264.

  71. Webb, C., Creek, R., Holt, W., King, G., and Young, I. 1986. A 65ns CMOS 1Mb DRAM. ISSCC Digest of Technical Papers, 262.

  72. Shah, A. H., Wang, C.-P., Womack, R. H., Gallia, J. D., Shichijo, H., Davis, H. E., Elahy, M., Banerjee, S. K., Pollack, G. P., Richardson, W. F., Bordelon, D. M., Malhi, S. D. S., Pilch, C., Tran, B., and Chatterjee, P. K. 1986. A 4Mb DRAM with cross-point trench transistor cell. ISSCC Digest of Technical Papers, 268.

  73. Kikuchi, M., Takahashi, S., Sato, Y., Inoue, Y. 1986. A 4Mb DRAM with half internal-voltage bitline precharge. ISSCC Digest of Technical Papers, 270.

  74. Furuyama, T., Ohsawa, T., Watanabe, Y., Ishiuchi, H., Tanaka, T., Ohuchi, K., Tango, H., Notori, K., and Ozawa, O. 1986. An experimental 4Mb CMOS DRAM. ISSCC Digest of Technical Papers, 272.

  75. Kobayashi, Y., Eguchi, H., Kudoh, O., Hara, T., Ooka, H., Sasaki, I., Andoh, M., and Tameda, M. 1985. A 10 μW stanby power 256K CMOS SRAM. ISSCC Digest of Technical Papers, 60.

  76. Akasaka, Y., and Kayano, S. 1985. A 45ns CMOS SRAM with tri-level world line. ISSCC Digest of Technical Papers, 62.

  77. Nagashima, S., Inagami, Y., Odaka, T., and Kawabe, S. 1984. Design consideration for a highspeed vector processor: the Hitachi S-810. ICCD, 238.

  78. Horikoshi H., and Inagami, Y. 1984. Japanese supercomputers—overview and perspective. ICCD, 227.

  79. Barkai, D., and Moriarty, K. J. M. ▪▪▪. Applications development on the CDC Cyber 205. 80. Klass, P. J. 1984. U.S. to gauge Japan computer speeds. Aviation Week & Space Technology (June 4).

  80. i/o ETA Systems. 1986 ETA System Publication, 2, 2.

    Google Scholar 

  81. Davis, D. B. 1984. Super computers: a strategic imperative. High Technology (May).

  82. The CRAY-2 computer system. Cray Research, Inc.

  83. 1986. Supercomputers hit their stride. Electronics, 44 (Mar. 10).

  84. 1985. Convex C-1 computer system. Publication 570-000180-000, Convex Computer Corporation, Richardson, Tex.

  85. Kobayashi, F., Anzai, A., Yamada, M., Takahashi, A., Yamazaki, S., and Toda, G. 1986. Packaging technologies for the ultrahigh-speed processor—Hitachi M-680H/M-682H. IEEE Electronic Components Conference, 571.

  86. Davidson, E. E. 1984. An electrical design methodology for multi-chip modules. ICCD, 573.

  87. Gheewala, T. R. 1984. System level comparison of high speed technologies. IEEE Int. Conf. on Computer Design: VLSI in Computers, ICCD, 245.

  88. Gilbert, B. K. 1984. Design and performance trade offs in the use of Si VLSI and gallium arsenide in high clockrate signal processors. IEEE Int. Conf. on Computer Design: VLSI in Computers, ICCD, 260. or90. Milutinovic, V., Fura, D., and Helbig, W. 1985. Impacts of GaAs on microprocessor architecture. IEEE Int. Conf. on Computer Design: VLSI in Computers, ICCD, 30.

  89. Dennard, R. H., Gaensslen, F. H., Kuhn, L., and Yu, H. N. 1972. Design of micron MOS switching devices. Presented IEDM, Washington, D.C., Dec.

    Google Scholar 

  90. Dennard, R. H., Gaensslen, F. H., Yu, H.-N., Rideout, V. L., Bassous, E., and Leblanc, A. R. 1974. Design of ion-implanted MOSFET's with very small physical dimensions. IEEE J. SolidState Circuits, SC-9, 256.

    Google Scholar 

  91. Brews, J. R., Fichtner, W., Nicollian, E. H., and Sze, S. M. 1980. Generalized guide for MOSFET miniaturization. IEEE Electron Device Letters, EDL-1, 2.

    Google Scholar 

  92. Chatterjee, P. K., Hunter, W. R., Holloway, T. C., and Lin, Y. T. 1980. The impact of scaling laws on the choice of n-channel or p-channel for MOS VLSI. IEEE Electron Device Lett., EDL-1, 220.

    Google Scholar 

  93. Baccarani, G., Wordeman, M. R., and Dennard, R. H. 1984. Generalized scaling theory and its application to a 1/4 micrometer MOSFET design. IEEE Trans. Electron Devices, ED-31, 452.

    Google Scholar 

  94. Solomon P. M., and Tang, D. D. 1979. Bipolar circuit scaling. ISSCC Digest Technical Papers, 86.

  95. Mead, C., and Conway, L. 1980. Introduction to VLSI Systems. Addison-Wesley, Reading, Mass.

    Google Scholar 

  96. Yu, H. N., Reisman, A., Osburn, C. M., and Critchlow, D. L. 1979. 1 μm MOSFET VLSI technology: part 1—an overview. IEEE J. Solid-State Circuits, SC-14, 240.

  97. Grobman, W., Luhn, H., Donohue, T., Speth, A., Wilson, A., Hatzakis, M., and Chang, T. H. P. 1972. 1 μm MOSFET VLSI technology: part VI—electron beam lithography. IEEE J. Solid-State Circuits, SC-14, 282.

    Google Scholar 

  98. Matsuda, T., Miyoshi, K., Yamaguchi, R., Moriya, S., Hosoya, T., and Harada, K. 1985. Submicrometer electron-beam direct writing technology for 1-Mbit DRAM fabrication. IEEE J. SolidState Circuits, SC-20, 88.

    Google Scholar 

  99. Bernacki, S. E. and Smith, H. I. 1974. X-ray lithography applied to silicon device fabrication. Proc. 6th Int. Conf. Electron, Ion Beam Sci. Technol., Electrochem. Soc., 34.

  100. Brown, W. L., Venkatesan, T., and Wagner, A., 1981. Ion beam lithography. Solid State Technol., 60 (Aug.).

  101. Pol, V. Bennewitz, J. H., Escher, G. C., Feldman, M., Firtion, V. A., Jewell, T. E., Wilcomb, B. E., Clemens, J. T. 1986. Laser based deep UV wafer stepper. SPIE Proceedings, 633.

  102. Ehrlich, D. J., Rothschild, M. 1986. Methods and materials for submicrometer-resolution excimer-laser projection patterning. 30th International Symposium on Electron, Ion, and Photon Beams (May), American Vacuum Society, to be published.

  103. Hatzakis, M. 1979. PMMA copolymers as high sensitivity electron resists. J. Vac. Sci. Technol., 16.

  104. Lin, B. J. 1979 J. Soc. Photo-Optical Instrum. Eng., 174, 114.

    Google Scholar 

  105. Lin, B. J., and Chang, T. H. P. 1979. Hybrid e-beam/deep UV exposure using portable conformable masking techniques. J. Vac. Sci. Technol., 16, 1669.

    Google Scholar 

  106. Lin, B. J. 1980. AX1350J as a deep-u.v. mask material. J. Electrochem Soc., 127, 202.

    Google Scholar 

  107. Lin, Y. C., Jones, S. K., and Fuller, G. 1983. Use of antireflective coating in bilayer resist process. Proceedings of 1983 International Symposium on Electron, Ion, and Photon Beams, American Vacuum Society.

  108. Alling, E., and Stauffer, C. 1985. Image reversal of positive photoresist: a new tool for advancing integrated circuit fabrication. SPIE Proceedings, 539, 194.

    Google Scholar 

  109. Jones, S. K., Chapman, R. C., and Pavelchek, E. K. 1987. Image reversal—applications for submicron processing. To be presented at First International Symposium on ULSI Science and Technology, May.

  110. Gijsen, R. M. R., Kroon, H. J. J., Vollenbroek, F. A., and Vervoordeldonk, R. 1986. A quantitative assessment of image reversal, a candidate for submicron process with improved linewidth control. SPIE Proceedings, 631, 108.

    Google Scholar 

  111. Klose, H., Sigush, R., and Arden, W. 1985. Image reversal of positive photoresist: characterization and modeling. IEEE Transactions on Electron Devices, ED-32, 1654.

    Google Scholar 

  112. Griffing, B. F., and West, P. R. 1982. Contrast enhanced photoresists—processing and modeling. Proceedings of the Sixth International Conference on Photopolymers, Ellenville, NY, Nov.

  113. Jones, S. K., Chapman, R. C., and Pavelchek, E. K. 1987. Image reversal—a practical approach to liftoff. Submitted to SPIE, May.

  114. Moritz, H. 1985. Optical single layer lift-off process. IEEE Transactions on Electron Devices, ED-32, 672.

    Google Scholar 

  115. Batchelder, T. 1981. A simple metal lift-off process (for 1 micron A1/5% Cu lines). SPIE Proceedings, 275, 143.

    Google Scholar 

  116. Jones, S. K., Chapman, R. C., Ho, Y.-S., and Bobbio, S., 1986. Pattern replication with a novolac/silicon polymer/polyester trilayer structure. Kodak Conference.

  117. Ephrath, L. M., and Bennett, R. S. 1982. Directional and selective etching of polysilicon and polycide. Proc. 1st Int. Symp. on Very Large Scale Integration Science and Technology, Electrochemical Society, 82–7, 108.

    Google Scholar 

  118. Thornton, J. A., and Penfold, A. S. 1978. In Thin Film Processes (J. L. Vossen and W. Kern, eds.), Academic Press, New York, p. 75.

    Google Scholar 

  119. Bobbio, S. M., and Ho, Y.-S. 1986. Very low voltage magnetron reactive ion etching. Electrochemical Society Fall Meeting, 86–2, 421.

    Google Scholar 

  120. Cho, K., Allen, W. R., Finstad, T. G., Chu, W. K., Liu, J., and Wortman, J. J., 1985. Channeling effect for low energy ion implantation in Si. Nuclear Instr. and Methods in Phys. Res., B7/8, 265.

    Google Scholar 

  121. Tsaur, B.-Y., and Anderson, C. H. Jr. 1983. J. Appl. Phys., 54, 6336.

    Google Scholar 

  122. Wilson, R. G. 1983. Boron, fluorine, and carrier profiles for B and BF2 implants into crystalline and amorphous Si. J. Appl. Phys., 54, 6879.

    Google Scholar 

  123. Seidel, T. E. 1983. Rapid thermal annealing of BF2 implanted, preamorphized silicon. IEEE Electron Dev. Letters, EDL-4, 353.

    Google Scholar 

  124. Sadana, D. K. Maszara, W., Wortman, J. J., Rozgonyi, G. A., and Chu, W. K. 1984. Germanium implantation into silicon: an alternate pre-amorphization/rapid thermal annealing procedure for shallow junction formation. J. Electrochem. Soc., 131, 942.

    Google Scholar 

  125. Seidel, T. E., Knoell, R., Poli, G., and Schwartz, B., 1985. Rapid thermal annealing of dopants implanted into preamorphized silicon. J. Appl. Phys., 58, 683.

    Google Scholar 

  126. Delfino, M., Sadana, D. K., and Morgan, A. E. 1986. Shallow junction formation by preamorphization with tin implantation. Accepted for publication in Appl. Phys. Lett.

  127. Delfino, M., Morgan A. E., and Sadana, D. K. 1986. Boron implantation into silicon amorphized by tin implantation. Accepted for publication in Nucl. Inst. Meth. B.

  128. Liu, J., Wortman, J. J., and Fair, R. B. 1985. Digest of the 41st Annual IEEE Device Research Conference, June.

  129. Powell, R. A., and Manion, M. L. 1986. Rapid thermal processing: a bibliography. Materials Research Society, Proc., 52, 441.

    Google Scholar 

  130. Chu, W. K. 1980. Appl. Phys. Lett., 36, 273.

    Google Scholar 

  131. Ligenza, J. R., and Spitzer, W. G. 1960. J. Phys Chem. Solids, 14, 131.

    Google Scholar 

  132. Ligenza, J. R. 1965. J. Appl. Phys., 36, 2703.

    Google Scholar 

  133. Ray, A. K., and Reisman, A. 1981. The formation of SiO2 in an RF generated oxygen plasma, I. the pressure range below 10 mTorr. J. Electrochem. Soc., 128, 2460.

    Google Scholar 

  134. Ray, A. K., and Reisman, A. 1981. Plasma oxide FET devices. J. Electrochem. Soc., 128, 2424.

    Google Scholar 

  135. Reisman, A. 1986. Assisted oxidation and annealing in VLSI and ULSI. Semiconductor Silicon, Electrochemical Society, 86–4, 364.

    Google Scholar 

  136. Zirinsky, S., and Crowder, B. L. 1977. Refractory silicides for high temperature compatible IC conductor lines. J. Electrochem. Soc., 124, 338C, 463 RNP.

    Google Scholar 

  137. Crowder, B. L., and Zirinsky, S. 1979. One micron MOSFET VLSI technology: part VII—metal suicide interconnect technology—A future perspective. IEEE Trans. Electron Devices, Ed-26, 369.

    Google Scholar 

  138. Muraka, S. P. 1979. Refractory silicides for low resistivity gates and interconnections. IEDM Tech. Digest, 454.

  139. Tsai, M. Y., Chao, H. H., Ephrath, L. M., Crowder, B. L., Cramer, A., Bennett, R. S., Lucchese, C. J., and Wordeman, M. R. 1981. One-micron polycide (WSi2 on poly-Si) MOSFET technology. J. Electrochem. Soc., 128, 2207.

    Google Scholar 

  140. Osburn, C. M., Tsai, M. Y., Roberts, S., Lucchese, C. J., and Ting, C. Y. 1982. High conductivity diffusions and gate regions using a self-aligned silicide technology. Proc. 1st Int. Symp. on VLSI Science and Technology, Electrochemical Society, 82–7, 213.

    Google Scholar 

  141. Shibata, T., Hieda, K., Sato, M., Konaka, M., Dang, R. L. M., and Iizuka, H. 1981. An optimally designed process for submicron MOSFET's. IEDM Tech. Digest, 647.

  142. Bryant, W. A. 1978. Kinetics of tungsten deposition by the reaction of WF6 and hydrogen. J. Electrochem. Soc., 125, 1534.

    Google Scholar 

  143. Broadbent, E. K., and Ramiller, C. L. 1984. Selective low pressure chemical vapor deposition of tungsten. J. Electrochem. Soc., 131, 1427.

    Google Scholar 

  144. Liaw, H. M., Reuss, R. H., Nguyen, H. T., and Woods, G. P. 1986. Surface morphology of selective epitaxial silicon. Proc. 5th Int. Symp. on Silicon Mater. Sci. and Tech., Electrochemical Society, 86–4, 260.

    Google Scholar 

  145. Sunami, H., Kure, T., Hashimoto, N., Itoh, K., Toyabe, T., and Asai, S. 1982. A corregated capacitor cell (CCC) for megabit dynamic memories. IEDM Tech. Digest, 806, and 1983. IEEE Electron Device Lett., EDL-4, 90.

  146. Wada, M., Hieda, K., and Watanabe, S. 1984. A folded capacitor cell (F. C. C.) for future megabit DRAMs. IEDM Tech. Digest, 244.

  147. Lasky, J. B. 1985. Silicon-on-insulator (SOI) by bonding and etch-back. IEDM Tech. Digest, 684.

  148. Frye, R. C., Griffith, J. E., andWong, Y. H. 1986. A field-assisted bonding process for silicon dielectric isolation. J. Electrochem. Soc., 133, 1673.

    Google Scholar 

  149. Locke, B. R., Donovan, R. P., Ensor, D. S., and Osburn, C. M. 1984. Semiconductor clean room particle spectra. First International Conference of the American Association for Aerosol Research, 669 (Sept.).

  150. Osburn, C. M. 1984. Aerosol control in semiconductor manufacturing. First International Conference of the American Association for Aerosol Research, 673 (Sept.).

  151. Totta, P. A., and Sopher, R. P. 1969. SLT device metallurgy and its monolithic extension. IBM J. Res. Dev., 13, 226.

    Google Scholar 

  152. Goldmann, L. S. 1969. Geometric optimization of controlled collapse interconnections. IBM J. Res. Dev., 13, 251.

    Google Scholar 

  153. Norris, K. C., and Landzberg, A. H. 1969. Reliability of controlled collapse interconnections. IBM J. Res. Dev., 13, 266.

    Google Scholar 

  154. Blodgett, A. Jr. 1980. Multi-layer ceramic, multichip module. IEEE Trans. Components, Hybrids Manuf. Technol., CHMT-3, 634.

    Google Scholar 

  155. Kishimoto, T., and Ohsake, T. 1986. VLSI packaging technique using liquid-cooled channels. IEEE BCC, 595.

  156. Kobayashi, F., Ogiue, K., Toda, G., and Wajima, M. 1984. Packaging technology for the supercomputer Hitachi S-810 array processor. Proc. of IEEE ECC, 379.

  157. Huang, C., Nunne, W., Spielberger, D., Mones, A., Fett, D., and Hampton, F. 1983. Silicon packaging—a new packaging technique. CICC, 142.

  158. Johnson, R. R. 1984. The significance of wafer scale integration in computer design. IEEE Int. Conf. Comp. Design, 101.

  159. Peltzer, D. L. 1983. Wafer-scale integration: the limits of VLSI? VLSI Design, 43 (Sept.).

  160. Neugebauer, C. A. 1985. Comparison of VLSI packaging approaches to wafer scale integration. IEEE CICC, 32.

  161. Ho, C. W. 1985. From single chip module to multichip module to WSI, the evolution of high performance computer packaging. Proc. of the Symp. on Electromigration of Metals and First Int. Symp. on Multilevel Metallization and Packaging, Electrochemical Society Proceedings, 85–6.

Download references

Author information

Authors and Affiliations

  1. Microelectronics Center of North Carolina, P.O. Box 12889, 27709, Research Triangle Park, NC, USA

    Carlton M. Osburn & Arnold Reisman

  2. Department of Electrical and Computer Engineering, North Carolina State University, 27695, Raleigh, NC, USA

    Carlton M. Osburn & Arnold Reisman

Authors
  1. Carlton M. Osburn
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Arnold Reisman
    View author publications

    You can also search for this author in PubMed Google Scholar

Rights and permissions

Reprints and permissions

About this article

Cite this article

Osburn, C.M., Reisman, A. Challenges in advanced semiconductor technology for high-performance and supercomputer applications. J Supercomput 1, 149–189 (1987). https://doi.org/10.1007/BF00128045

Download citation

  • Issue Date:

  • DOI: https://doi.org/10.1007/BF00128045

Keywords

Search

Navigation