Abstract
The field of IC technology grows every day and it plays a decisive role in a day to day activity. One of the most emerging fields is biomedical. This field is getting wider and the size of the devices becomes reduced from ECG machines to portable medical devices. Nowadays wearable devices and implantable biomedical devices on the body captures the biosignals and convert it as potential signals to measure the variation and the devices which are connected to the cloud using IoT technology is helpful to digest the types of problem with less time and better accuracy. So the biopotential signal has to be shared and processed between the memory and the processor. The more sensible processor has to collect the required data from the associated memory to make an agile response. Hence this paper describes the logic and criteria on choosing the most prominent memory SRAM. The SRAM architecture in this paper is discussed based on transistors count like 5T, 6T, 8T,9T, and 10T. The no of transistors on the SRAM used to decide the level of leakage power and other junction power and also the die area it occupies. Here the 5T SRAM shows the notable variations in the delay and has a good level on leakage power and dynamic power reduction. Henceforth using the proposed SRAM in wearable biomedical devices could cause betterment in speed, agility in response, and consume less power. This SRAM can be used to access denser data with less delay time.
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Dinesh Kumar, J.R., Ganesh Babu, C., Balaji, V.R., Priyadharsini, K., Karthi, S.P. (2021). Performance Investigation of Various SRAM Cells for IoT Based Wearable Biomedical Devices. In: Ranganathan, G., Chen, J., Rocha, Á. (eds) Inventive Communication and Computational Technologies. Lecture Notes in Networks and Systems, vol 145. Springer, Singapore. https://doi.org/10.1007/978-981-15-7345-3_49
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DOI: https://doi.org/10.1007/978-981-15-7345-3_49
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