Abstract
SRAM cells are known for their high speed operation and low power consumption, and have got considerable attention in research works. Different cell topologies have been developed and proposed to improve various important parameters of the cell to make them favorable for practical operations. These parameters include power consumption, leakage current, stability and speed of response. The paper here describes new 8T SRAM cell which is quite different from recently proposed 8T cells. The modification has been done to increase the speed of cell by reducing the write access time. The other parameters especially power consumption of cell has also been kept in consideration.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
Similar content being viewed by others
References
Nehra, V., Singh, R., Shukla, N., Birla, S., Kumar, M., Goel A., Simulation & Analysis of 8T SRAM Cell’s Stability at Deep Sub-Micron CMOS Technology for Multimedia Applications, Canadian Journal on Electrical and Electronics Engineering, 3, 11-16 (2012).
Hamzaoglu, F., Zhang, K., Wang, Y., Ahn, H.J., Bhattacharya, U., Chen, Z., Ng, Y.G., Pavlov, A., Smits, K., Bohr, M., A 3.8 GHz 153 Mb SRAM Design With Dynamic, Stability Enhancement and Leakage Reduction in 45 nm High-k Metal Gate CMOS Technology, IEEE Journal Of Solid-State Circuits, 44, 148-154, 2009.
Kam, T., Rawat, S., Kirkpatrick, D., Roy, R., Spirakis, G.S., Sherwani, N., Peterson, C., EDA Challenges Facing Future Microprocessor Design, IEEE Transactions on Computer-Aided Design, 19, 1498-1506, 2000.
Khandelwal, V., and Srivastava, A., Leakage Control Through Fine-Grained Placement and Sizing of Sleep Transistors, IEEE Transactions On Computer-Aided Design Of Integrated Circuits And Systems, 26, 1246-1255, 2007.
Zhu, H. and Kursun, K., Data Stability Enhancement Techniques for Nanoscale Memory Circuits: 7T Memory Design Tradeoffs and Options in 80 nm UMC CMOS Technology, SoC Design International Conference (ISOCC), 158-161, 2010.
Charan Thondapu, Praveen Elakkumanan, and Ramalingam Sridhar, RG-SRAM: A Low Gate Leakage Memory Design, Proceedings of the IEEE Computer Society Annual Symposium on VLSI, New Frontiers in VLSI Design, 295-296, 2005.
McArthur, R., Making Use of Gate Charge Information in MOSFET and IGBT Data Sheets, Advanced Power Technology, 1-8, 2001.
Seevinck, E., Van Beers, P.J., Ontrop, H., Current mode techniques for high speed VLSI circuits with application to current sense amplifiers for CMOS SRAMs, IEEE Journal of Solid Sstate Circuits, 26.4, 525-536, 1991.
Dutta, S., Nag, S., Roy, K., ASAP: A Transistor Sizing tool For Speed, Area and Power Optimization of Static CMOS Circuits, IEEE International Symposium on Circuits and Systems, 61-64, 1994.
Kumar, A., Shalini, S., Khan, I.A., Optimized SRAM Cell Design for High Speed and Low Power Application, IEEE Conference on Information and Communication Technologies (WICT), 1357-1362, 2011.
Ahmadimehr, A.R., Evrahimi, B., Afzali-Kusha, A., A High Speed Sub-Threshold SRAM Cell Design, IEEE Conference on Quality of Electronic Design (ASQED), 9-13, 2009.
Tzartzanis, N., and Athas, W.C., Energy Recovery for The Design of High Speed Low Power Static RAMs, IEEE International Symposium on Low Power Electronics and Design, 55-60, 1996.
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2013 Springer India
About this paper
Cite this paper
Johri, R., Kushwah, R.S., Singh, R., Akashe, S. (2013). Modeling and Simulation of High Speed 8T SRAM Cell. In: Bansal, J., Singh, P., Deep, K., Pant, M., Nagar, A. (eds) Proceedings of Seventh International Conference on Bio-Inspired Computing: Theories and Applications (BIC-TA 2012). Advances in Intelligent Systems and Computing, vol 202. Springer, India. https://doi.org/10.1007/978-81-322-1041-2_21
Download citation
DOI: https://doi.org/10.1007/978-81-322-1041-2_21
Published:
Publisher Name: Springer, India
Print ISBN: 978-81-322-1040-5
Online ISBN: 978-81-322-1041-2
eBook Packages: EngineeringEngineering (R0)