Abstract
A novel algorithmic approach for a global routing solution for VLSI circuits is proposed in this paper. Instead of following the traditional Steiner tree approach towards global routing, we have used a congestion sensing path laying approach. We introduce the concept of detouring of net segments running through heavily congested edges. The technique brings down the congestion of edges, to meet the constraints of edge capacity, by detouring the net segments through sparsely populated edges. Our approach has been implemented and tested on the ISPD 98 benchmark circuits and has achieved results comparable to other global routers when congestion minimization and wire length minimization are taken into consideration.
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Mukherjee, S., Patra, J., Roy, S. (2013). Congestion Balancing Global Router. In: Gaur, M.S., Zwolinski, M., Laxmi, V., Boolchandani, D., Sing, V., Sing, A.D. (eds) VLSI Design and Test. Communications in Computer and Information Science, vol 382. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-42024-5_27
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DOI: https://doi.org/10.1007/978-3-642-42024-5_27
Publisher Name: Springer, Berlin, Heidelberg
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