Abstract
System-on-chip integrate an increasing amount of processing elements and on-chip communication is of particular importance. Rising communication rates with varying delays require efficient techniques to signal events related to the on-chip communication to the application software. While latencies are commonly hidden by multithreading, the signaling of events is usually done by polling or interrupts. With rising rates of such events the classic techniques expose an increasing software overhead that becomes significantly important.
In this paper we present the concept of hardware-based operating system queue manipulation (HW-OSQM) to offload the process of event signaling. The concept is implemented as a flexible hardware accelerator which integrates with the communication hardware and autonomously manipulates the queue data structures of the operating system. It eliminates the associated software overhead and utilizes small additional resources while allowing for the required flexibility. The performance improvement shows that HW-OSQM can nearly eliminate any overhead in software.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
Similar content being viewed by others
References
van Berkel, C.H.K.: Multi-core for mobile phones. In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2009, pp. 1260–1265. European Design and Automation Association, Leuven (2009)
Langendoen, K., et al.: Integrating Polling, Interrupts, and Thread Management. In: Proceedings of the 6th Symposium on the Frontiers of Massively Parallel Computation, pp. 13–22. IEEE Computer Society (1996)
Goglin, B., Furmento, N.: Finding a tradeoff between host interrupt load and MPI latency over Ethernet. In: IEEE International Conference on Cluster Computing and Workshops, CLUSTER 2009, August 31-September 4, pp. 1–9 (2009)
Kariniemi, H., Nurmi, J.: High-performance NoC Interface with interrupt batching for Micronmesh MPSoC prototype platform on FPGA. In: NORCHIP, pp. 1–6 (November 2010)
Castrillon, J., et al.: Task management in MPSoCs: an ASIP approach. In: Proceedings of the 2009 International Conference on Computer-Aided Design, ICCAD 2009, pp. 587–594. ACM, New York (2009)
Scheler, F., et al.: Parallel, hardware-supported interrupt handling in an event-triggered real-time operating system. In: Proceedings of the 2009 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2009, pp. 167–174. ACM, New York (2009)
Nácul, A.C., Regazzoni, F., Lajolo, M.: Hardware scheduling support in SMP architectures. In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2007, San Jose, CA, USA, EDA Consortium, pp. 642–647 (2007)
Bolychevsky, A., Jesshope, C., Muchnick, V.: Dynamic scheduling in RISC architectures. IEE Proceedings Computers and Digital Techniques 143(5), 309–317 (1996)
Bousias, K., et al.: Implementation and evaluation of a microthread architecture. J. Syst. Archit. 55, 149–161 (2009)
Hicks, M., van Tol, M., Jesshope, C.: Towards scalable I/O on a many-core architecture. In: 2010 International Conference on Embedded Computer Systems (SAMOS), pp. 341–348 (July 2010)
INMOS Limited: Transputer Reference Manual. Prentice Hall (1992)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2013 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Wallentowitz, S., Wild, T., Herkersdorf, A. (2013). HW-OSQM: Reducing the Impact of Event Signaling by Hardware-Based Operating System Queue Manipulation. In: Kubátová, H., Hochberger, C., Daněk, M., Sick, B. (eds) Architecture of Computing Systems – ARCS 2013. ARCS 2013. Lecture Notes in Computer Science, vol 7767. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-36424-2_24
Download citation
DOI: https://doi.org/10.1007/978-3-642-36424-2_24
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-36423-5
Online ISBN: 978-3-642-36424-2
eBook Packages: Computer ScienceComputer Science (R0)