Years and Authors of Summarized Original Work
1996; Pan, Liu
1998; Pan, Liu
1998; Pan, Lin
Problem Definition
One of the key steps in a VLSI design flow is technology mapping that converts a Boolean network of technology-independent logic gates and D-flipflops (FFs) into an equivalent one comprised of cells from a technology library [1, 4]. Technology mapping can be formulated as a covering problem where logic gates are covered by cells from the technology library. For ease of discussion, it is assumed that the cell library contains only one cell, a K-input lookup table (K-LUT) with one unit of delay. A K-LUT can implement any Boolean function with up to K inputs as is the case in field-programmable gate arrays (FPGAs) [1, 3].
Figure 1 shows an example of technology mapping. The original network in (1) with three FFs and four gates is covered by three 3-input cones as indicated in (2). The corresponding mapping solution using 3-LUTs is shown in (3). Note that gate iis covered by two...
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Recommended Reading
Cong J, Ding Y (1994) FlowMap: an optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs. IEEE Trans Comput Aided Des Integr Circuits Syst 13(1):1–12
Cong J, Wu C (1997) FPGA synthesis with retiming and pipelining for clock period minimization of sequential circuits. In: ACM/IEEE design automation conference, Anaheim
Cong J, Wu C, Ding Y (1999) Cut ranking and pruning: enabling a general and efficient FPGA mapping solution. In: ACM international symposium on field-programmable gate arrays, Monterey
Keutzer K (1987) DAGON: technology binding and local optimization by DAG matching. In: ACM/IEEE design automation conference, Miami Beach
Leiserson CE, Saxe JB (1991) Retiming synchronous circuitry. Algorithmica 6:5–35
Mishchenko A, Chatterjee S, Brayton R, Pan P (2006) Integrating logic synthesis, technology mapping, and retiming. ERL technical report, EECS Department, UC Berkeley
Pan P (1997) Continuous retiming algorithms and applications. In: IEEE international conference on computer design, Austin
Pan P, Lin CC (1998) A new retiming-based technology mapping algorithm for LUT-based FPGAs. In: ACM international symposium on field-programmable gate arrays, Monterey
Pan P, Liu CL (1996) Optimal clock period FPGA technology mapping for sequential circuits. In: ACM/IEEE design automation conference, Las Vegas
Pan P, Liu CL (1998) Optimal clock period FPGA technology mapping for sequential circuits. ACM Trans Des Autom Electron Syst 3(3):437–462
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Pan, P. (2014). Sequential Circuit Technology Mapping. In: Kao, MY. (eds) Encyclopedia of Algorithms. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-27848-8_364-2
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DOI: https://doi.org/10.1007/978-3-642-27848-8_364-2
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