Abstract
This paper presents the first results of our work to research and develop new reconfigurable circuits and topologies based on Magnetic RAM (MRAM) memory elements. This work proposes a coarse-grained reconfigurable array using MRAM. A coarse-grained array, where each reconfigurable element computes on 4-bit or larger input words, is more suitable to execute data-oriented algorithms and is more able to exploit large amounts of operation-level parallelism than common fine-grained architectures. The architecture is organized as a one-dimensional array of programmable ALU and the configuration bits are stored in MRAM. MRAM provide non-volatility with cell areas and with access speeds comparable to those of SRAM and with lower process complexity than FLASH memory. MRAM can also be efficiently organized as multi-context memories.
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References
Third Generation Non-Volatile FPGAs Enable System on Chip Functionality. White Paper, Lattice Semiconductor Corporation (2007)
Nageldinger, U.: Coarse-grained Reconfigurable Architectures Design Space Exploration. Ph.D Dissertation, C.S Department, University of Kaiserslautern (2001)
Bruchon, N., Cambon, G., Torres, L., Sassatelli, G.: Magnetic remanent memory structures for dynamically reconfigurable FPGA. In: International Conference on Field Programmable Logic and Applications, pp. 687–690. IEEE, Los Alamitos (2005)
Bruchon, N., Torres, L., Sassatelli, G., Cambon, G.: Magnetic tunnelling junction based FPGA. In: 2006 ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, pp. 123–130. ACM, New York (2006)
Hartenstein, R.: A Decade of Reconfigurable Computing: a Visionary Retrospective. In: Conference on Design, Automation and Test in Europe, pp. 642–649. IEEE, Los Alamitos (2001)
Zain-ul-Abdin, Svensson, B.: Evolution in architectures and programming methodologies of coarse-grained reconfigurable computing. Microprocessors and Microsystems 33(3), 161–178 (2009)
Ebeling, C.: The General Rapid Architecture Description. Tech. Rep. UW-CSE-02-06-02, University of Washington (2002)
Goldstein, S.C., Schmit, H., Moe, M., Budiu, M., Cadambi, S., Taylor, R.R., Laufer, R.: PipeRench: A Coprocessor for Streaming Multimedia Acceleration. In: 26th International Symposium on Computer Architecture (ISCA 1999), pp. 28–39. IEEE, Los Alamitos (1999)
Bruchon, N., Torres, L., Sassatelli, G., Cambon, G.: New non-volatile FPGA concept using Magnetic Tunneling Junction. In: IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures (ISVLSI 2006), pp. 269–276. IEEE, Los Alamitos (2006)
Zhao, W., Belhaire, E., Dieny, B., Prenat, G., Chappert, C.: TAS-MRAM based Non-volatile FPGA logic circuit. In: International Conference on Field-Programmable Technology (ICFPT 2007), pp. 153–160. IEEE, Los Alamitos (2007)
Guillemenet, Y., Torres, L., Sassatelli, G., Bruchon, N., Hassoune, I.: A non-volatile run-time FPGA using thermally assisted switching MRAMS. In: International Conference on Field-Programmable Logic and Applications (FPL 2008), pp. 421–426. IEEE, Los Alamitos (2008)
Zhao, W., Belhaire, E., Mistral, Q., Nicolle, E., Devolder, T., Chappert, C.: Integration of Spin-RAM technology in FPGA circuits. In: 8th International Conference on Solid-State and Integrated Circuit Technology (ICSICT 2006), pp. 799–802. IEEE, Los Alamitos (2006)
DeBrosse, J., Arndt, C., Barwin, C., Bette, A., Gogl, D., Gow, E., Hoenigschmid, H., Lammers, S., Lamorey, M., Lu, Y., Maffitt, T., Maloney, K., Obermeyer, W., Sturm, A., Viehmann, H., Willmott, D., Wood, M., Gallagher, W.J., Mueller, G., Sitaram, A.R.: A 16Mb MRAM featuring bootstrapped write drivers. In: 2004 Symposium on VLSI Circuits, pp. 454–457. IEEE, Los Alamitos (2004)
Silva, V., Oliveira, L.B., Fernandes, J.R., Véstias, M.P., Neto, H.C.: Run-Time Reconfigurable Array using Magnetic RAM. In: 12th EUROMICRO Conference on Digital System Design, DSD 2009 (2009)
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Silva, V., Fernandes, J., Neto, H. (2010). Reconfigurable Circuits Using Magnetic Tunneling Junction Memories. In: Camarinha-Matos, L.M., Pereira, P., Ribeiro, L. (eds) Emerging Trends in Technological Innovation. DoCEIS 2010. IFIP Advances in Information and Communication Technology, vol 314. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-11628-5_61
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DOI: https://doi.org/10.1007/978-3-642-11628-5_61
Publisher Name: Springer, Berlin, Heidelberg
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