Abstract
This paper presents a Design-for-Test (DfT) approach for folded ADCs. A sensor DfT circuit is designed to sample several internal ADC test points at the same time, so that, by computing the relative deviation among them the presence of defects can be detected. A fault evaluation is done considering a behavioral model to compare the coverage of the proposed test approach with a functional test. Afterwards, a fault simulation is used on a transistor level implementation of the ADC to establish the optimum threshold limits for the DfT circuit that maximize the fault coverage figure.
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Lechuga, Y., Mozuelos, R., Martínez, M., Bracho, S. (2010). Structural DfT Strategy for High-Speed ADCs. In: Camarinha-Matos, L.M., Pereira, P., Ribeiro, L. (eds) Emerging Trends in Technological Innovation. DoCEIS 2010. IFIP Advances in Information and Communication Technology, vol 314. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-11628-5_59
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DOI: https://doi.org/10.1007/978-3-642-11628-5_59
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-11627-8
Online ISBN: 978-3-642-11628-5
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