Fully Utilized and Low Design Effort Architecture for H.264/AVC Intra Predictor Generation

Fully exploiting the spatial feature of image makes H.264/ AVC standard superior in intra prediction part. However, when hardware is considered, full support of all intra modes will cause high design effort, especially for large image size. In this paper, we propose a low design effort solution for intra predictor generation, which is the most significant part in intra engine. Firstly, one parallel processing flow is given out, which achieves 37.5% reduction of processing time. Secondly, a fully utilized predictor generation architecture is given out, which saves 77.5% cycles of original one. With 30.11k gates at 200MHz, our design can support full-mode intra prediction for real-time processing of 4k×2k@60fps.

Authors and Affiliations

1. Graduate School of Information, Production and Systems, Waseda University, Japan

   Yiqing Huang, Qin Liu & Takeshi Ikenaga

Editors and Affiliations

1. University of Oldenburg, Germany

   Susanne Boll

2. University of Texas at San Antonio,, TX, San Antonio, USA

   Qi Tian

3. Microsoft Research Asia, Beijing, P.R. China

   Lei Zhang

4. Southwest University, Beibei, Chongqing, China

   Zili Zhang

5. School of Engineering and Information Technology, Deakin University, 221 Burwood Highway, Vic, 3125, Australia

   Yi-Ping Phoebe Chen

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